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IDT71V421S35TFGI8 PDF预览

IDT71V421S35TFGI8

更新时间: 2024-11-07 06:48:43
品牌 Logo 应用领域
艾迪悌 - IDT 静态存储器
页数 文件大小 规格书
15页 133K
描述
Multi-Port SRAM, 2KX8, 35ns, CMOS, PQFP64

IDT71V421S35TFGI8 数据手册

 浏览型号IDT71V421S35TFGI8的Datasheet PDF文件第2页浏览型号IDT71V421S35TFGI8的Datasheet PDF文件第3页浏览型号IDT71V421S35TFGI8的Datasheet PDF文件第4页浏览型号IDT71V421S35TFGI8的Datasheet PDF文件第5页浏览型号IDT71V421S35TFGI8的Datasheet PDF文件第6页浏览型号IDT71V421S35TFGI8的Datasheet PDF文件第7页 
IDT71V321S/L  
IDT71V421S/L  
HIGH SPEED 3.3V  
2K X 8 DUAL-PORT  
STATIC RAM WITH INTERRUPTS  
Features  
On-chip port arbitration logic (IDT71V321 only)  
High-speed access  
BUSY output flag on IDT71V321; BUSY input on IDT71V421  
Fully asynchronous operation from either port  
Battery backup operation2V data retention (L only)  
TTL-compatible, single 3.3V power supply  
Available in 52-pin PLCC, 64-pin TQFP and STQFP  
packages  
Industrial temperature range (–40°C to +85°C) is available  
for selected speeds  
Green parts available, see ordering information  
– Commercial: 25/35/55ns (max.)  
Industrial: 25ns (max.)  
Low-power operation  
IDT71V321/IDT71V421S  
Active: 325mW (typ.)  
Standby: 5mW (typ.)  
IDT71V321/V421L  
Active: 325mW (typ.)  
Standby: 1mW (typ.)  
Two INT flags for port-to-port communications  
MASTER IDT71V321 easily expands data bus width to 16-  
or-more-bits using SLAVE IDT71V421  
FunctionalBlockDiagram  
OE  
R
R
OE  
L
CE  
R/W  
CEL  
R
R/W  
L
I/O0L- I/O7L  
I/O0R-I/O7R  
I/O  
Control  
I/O  
Control  
(1,2)  
(1,2)  
BUSYR  
BUSY  
L
A
10L  
A
A
10R  
0R  
Address  
Decoder  
MEMORY  
ARRAY  
Address  
Decoder  
A
0L  
11  
11  
ARBITRATION  
and  
INTERRUPT  
LOGIC  
CE  
OE  
R/W  
L
CE  
OE  
R/W  
R
R
L
R
L
(2)  
(2)  
L
INTR  
INT  
3026 drw 01  
NOTES:  
1. IDT71V321 (MASTER): BUSY is an output. IDT71V421 (SLAVE): BUSY is input.  
2. BUSY and INT are totem-pole outputs.  
AUGUST 2006  
1
DSC-3026/10  
©2006IntegratedDeviceTechnology,Inc.  

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