Datasheet > IDT71V421S35JG8

IDT71V421S35JG8

更新时间： 2024-11-18 18:40:27

品牌	Logo	应用领域
艾迪悌 - IDT		静态存储器
页数	文件大小	规格书
15页	133K
描述
Multi-Port SRAM, 2KX8, 35ns, CMOS, PQCC52

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中文翻译

获取价格

技术参数
数据手册

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IDT71V421S35JG8 技术参数

是否无铅：	不含铅	是否Rohs认证：	符合
生命周期：	Obsolete	包装说明：	QCCJ, LDCC52,.8SQ
Reach Compliance Code：	compliant	风险等级：	5.84
Base Number Matches：	1

IDT71V421S35JG8 数据手册

IDT71V321S/L

IDT71V421S/L

HIGH SPEED 3.3V

2K X 8 DUAL-PORT

STATIC RAM WITH INTERRUPTS

Features

◆

On-chip port arbitration logic (IDT71V321 only)

High-speed access

◆

BUSY output flag on IDT71V321; BUSY input on IDT71V421

Fully asynchronous operation from either port

Battery backup operation—2V data retention (L only)

TTL-compatible, single 3.3V power supply

Available in 52-pin PLCC, 64-pin TQFP and STQFP

packages

Industrial temperature range (–40°C to +85°C) is available

for selected speeds

Green parts available, see ordering information

– Commercial: 25/35/55ns (max.)

– Industrial: 25ns (max.)

Low-power operation

– IDT71V321/IDT71V421S

— Active: 325mW (typ.)

— Standby: 5mW (typ.)

– IDT71V321/V421L

— Active: 325mW (typ.)

— Standby: 1mW (typ.)

◆

Two INT flags for port-to-port communications

MASTER IDT71V321 easily expands data bus width to 16-

◆

or-more-bits using SLAVE IDT71V421

FunctionalBlockDiagram

R/W

CEL

R/W

I/O0L- I/O7L

I/O0R-I/O7R

I/O

Control

I/O

Control

(1,2)

BUSYR

BUSY

10L

10R

Address

Decoder

MEMORY

ARRAY

Address

Decoder

ARBITRATION

and

INTERRUPT

LOGIC

R/W

(2)

INTR

INT

3026 drw 01

NOTES:

1. IDT71V321 (MASTER): BUSY is an output. IDT71V421 (SLAVE): BUSY is input.

2. BUSY and INT are totem-pole outputs.

AUGUST 2006

DSC-3026/10

12 3 4 5 6 7...15

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