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IDT71V321S35TF9 PDF预览

IDT71V321S35TF9

更新时间: 2024-11-04 15:34:43
品牌 Logo 应用领域
艾迪悌 - IDT 静态存储器内存集成电路
页数 文件大小 规格书
14页 129K
描述
Dual-Port SRAM, 2KX8, 35ns, CMOS, PQFP64, STQFP-64

IDT71V321S35TF9 技术参数

是否无铅: 含铅是否Rohs认证: 不符合
生命周期:Obsolete零件包装代码:QFP
包装说明:LFQFP,针数:64
Reach Compliance Code:compliantECCN代码:EAR99
HTS代码:8542.32.00.41风险等级:5.78
最长访问时间:35 ns其他特性:BATTERY BACKUP;AUTOMATIC POWER DOWN
JESD-30 代码:S-PQFP-G64JESD-609代码:e0
长度:10 mm内存密度:16384 bit
内存集成电路类型:DUAL-PORT SRAM内存宽度:8
湿度敏感等级:3功能数量:1
端子数量:64字数:2048 words
字数代码:2000工作模式:ASYNCHRONOUS
最高工作温度:70 °C最低工作温度:
组织:2KX8封装主体材料:PLASTIC/EPOXY
封装代码:LFQFP封装形状:SQUARE
封装形式:FLATPACK, LOW PROFILE, FINE PITCH并行/串行:PARALLEL
峰值回流温度(摄氏度):240认证状态:Not Qualified
座面最大高度:1.6 mm最大供电电压 (Vsup):3.6 V
最小供电电压 (Vsup):3 V标称供电电压 (Vsup):3.3 V
表面贴装:YES技术:CMOS
温度等级:COMMERCIAL端子面层:TIN LEAD
端子形式:GULL WING端子节距:0.5 mm
端子位置:QUAD处于峰值回流温度下的最长时间:20
宽度:10 mmBase Number Matches:1

IDT71V321S35TF9 数据手册

 浏览型号IDT71V321S35TF9的Datasheet PDF文件第2页浏览型号IDT71V321S35TF9的Datasheet PDF文件第3页浏览型号IDT71V321S35TF9的Datasheet PDF文件第4页浏览型号IDT71V321S35TF9的Datasheet PDF文件第5页浏览型号IDT71V321S35TF9的Datasheet PDF文件第6页浏览型号IDT71V321S35TF9的Datasheet PDF文件第7页 
IDT71V321S/L  
IDT71V421S/L  
HIGH SPEED 3.3V  
2K X 8 DUAL-PORT  
STATIC RAM WITH INTERRUPTS  
ꢀeatures  
MASTER IDT71V321 easily expands data bus width to 16-  
or-more-bits using SLAVE IDT71V421  
High-speed access  
– Commercial: 25/35/55ns (max.)  
Industrial: 25ns (max.)  
Low-power operation  
On-chip port arbitration logic (IDT71V321 only)  
BUSY output flag on IDT71V321; BUSY input on IDT71V421  
Fully asynchronous operation from either port  
Battery backup operation2V data retention (L only)  
TTL-compatible, single 3.3V power supply  
Available in 52-pin PLCC, 64-pin TQFP and STQFP  
packages  
IDT71V321/IDT71V421S  
Active: 325mW (typ.)  
Standby: 5mW (typ.)  
IDT71V321/V421L  
Active: 325mW (typ.)  
Standby: 1mW (typ.)  
Industrial temperature range (–40°C to +85°C) is available  
for selected speeds  
Two INT flags for port-to-port communications  
ꢀunctionalBlockDiagram  
OER  
OEL  
CER  
CEL  
R/WR  
R/WL  
I/O0L- I/O7L  
I/O0R-I/O7R  
I/O  
Control  
I/O  
Control  
(1,2)  
(1,2)  
BUSYR  
BUSYL  
A10L  
A0L  
A10R  
Address  
Decoder  
MEMORY  
ARRAY  
Address  
Decoder  
A0R  
11  
11  
ARBITRATION  
and  
INTERRUPT  
LOGIC  
CEL  
OEL  
CER  
OER  
R/WR  
R/WL  
(2)  
(2)  
INTL  
INTR  
3026 drw 01  
NOTES:  
1. IDT71V321 (MASTER): BUSY is an output. IDT71V421 (SLAVE): BUSY is input.  
2. BUSY and INT are totem-pole outputs.  
AUGUST 2001  
1
DSC-3026/8  
©2001IntegratedDeviceTechnology,Inc.  

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