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IDT71V321L25JI PDF预览

IDT71V321L25JI

更新时间: 2024-11-03 22:10:31
品牌 Logo 应用领域
艾迪悌 - IDT 存储内存集成电路静态存储器
页数 文件大小 规格书
14页 130K
描述
HIGH-SPEED 3.3V 2K x 8 DUAL-PORT STATIC RAM WITH INTERRUPT

IDT71V321L25JI 技术参数

是否无铅:含铅是否Rohs认证:不符合
生命周期:Obsolete零件包装代码:LCC
包装说明:PLASTIC, LCC-52针数:52
Reach Compliance Code:not_compliantECCN代码:EAR99
HTS代码:8542.32.00.41风险等级:5.71
Is Samacsys:N最长访问时间:25 ns
I/O 类型:COMMONJESD-30 代码:S-PQCC-J52
JESD-609代码:e0长度:19.1262 mm
内存密度:16384 bit内存集成电路类型:DUAL-PORT SRAM
内存宽度:8湿度敏感等级:3
功能数量:1端口数量:2
端子数量:52字数:2048 words
字数代码:2000工作模式:ASYNCHRONOUS
最高工作温度:85 °C最低工作温度:-40 °C
组织:2KX8输出特性:3-STATE
封装主体材料:PLASTIC/EPOXY封装代码:QCCJ
封装等效代码:LDCC52,.8SQ封装形状:SQUARE
封装形式:CHIP CARRIER并行/串行:PARALLEL
峰值回流温度(摄氏度):225电源:3.3 V
认证状态:Not Qualified座面最大高度:4.57 mm
最大待机电流:0.004 A最小待机电流:2 V
子类别:SRAMs最大压摆率:0.13 mA
最大供电电压 (Vsup):3.6 V最小供电电压 (Vsup):3 V
标称供电电压 (Vsup):3.3 V表面贴装:YES
技术:CMOS温度等级:INDUSTRIAL
端子面层:Tin/Lead (Sn85Pb15)端子形式:J BEND
端子节距:1.27 mm端子位置:QUAD
处于峰值回流温度下的最长时间:30宽度:19.1262 mm
Base Number Matches:1

IDT71V321L25JI 数据手册

 浏览型号IDT71V321L25JI的Datasheet PDF文件第2页浏览型号IDT71V321L25JI的Datasheet PDF文件第3页浏览型号IDT71V321L25JI的Datasheet PDF文件第4页浏览型号IDT71V321L25JI的Datasheet PDF文件第5页浏览型号IDT71V321L25JI的Datasheet PDF文件第6页浏览型号IDT71V321L25JI的Datasheet PDF文件第7页 
IDT71V321S/L  
IDT71V421S/L  
HIGH SPEED 3.3V  
2K X 8 DUAL-PORT  
STATIC RAM WITH INTERRUPTS  
ꢀeatures  
MASTER IDT71V321 easily expands data bus width to 16-  
or-more-bits using SLAVE IDT71V421  
High-speed access  
– Commercial: 25/35/55ns (max.)  
Industrial: 25ns (max.)  
Low-power operation  
On-chip port arbitration logic (IDT71V321 only)  
BUSY output flag on IDT71V321; BUSY input on IDT71V421  
Fully asynchronous operation from either port  
Battery backup operation2V data retention (L only)  
TTL-compatible, single 3.3V power supply  
Available in 52-pin PLCC, 64-pin TQFP and STQFP  
packages  
IDT71V321/IDT71V421S  
Active: 325mW (typ.)  
Standby: 5mW (typ.)  
IDT71V321/V421L  
Active: 325mW (typ.)  
Standby: 1mW (typ.)  
Industrial temperature range (–40°C to +85°C) is available  
for selected speeds  
Two INT flags for port-to-port communications  
ꢀunctionalBlockDiagram  
OER  
OEL  
CER  
CEL  
R/WR  
R/WL  
I/O0L- I/O7L  
I/O0R-I/O7R  
I/O  
Control  
I/O  
Control  
(1,2)  
(1,2)  
BUSYR  
BUSYL  
A10L  
A0L  
A10R  
Address  
Decoder  
MEMORY  
ARRAY  
Address  
Decoder  
A0R  
11  
11  
ARBITRATION  
and  
INTERRUPT  
LOGIC  
CEL  
OEL  
CER  
OER  
R/WR  
R/WL  
(2)  
(2)  
INTL  
INTR  
3026 drw 01  
NOTES:  
1. IDT71V321 (MASTER): BUSY is an output. IDT71V421 (SLAVE): BUSY is input.  
2. BUSY and INT are totem-pole outputs.  
AUGUST 2001  
1
DSC-3026/8  
©2001IntegratedDeviceTechnology,Inc.  

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