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IDT71V2578YSA150BQG PDF预览

IDT71V2578YSA150BQG

更新时间: 2024-11-21 21:10:55
品牌 Logo 应用领域
艾迪悌 - IDT 静态存储器内存集成电路
页数 文件大小 规格书
22页 233K
描述
Cache SRAM, 256KX18, 3.8ns, CMOS, PBGA165, GREEN, FBGA-165

IDT71V2578YSA150BQG 技术参数

是否Rohs认证: 符合生命周期:Obsolete
零件包装代码:BGA包装说明:GREEN, FBGA-165
针数:165Reach Compliance Code:compliant
ECCN代码:3A991.B.2.AHTS代码:8542.32.00.41
风险等级:5.8最长访问时间:3.8 ns
其他特性:PIPELINED ARCHITECTUREJESD-30 代码:R-PBGA-B165
JESD-609代码:e1长度:15 mm
内存密度:4718592 bit内存集成电路类型:CACHE SRAM
内存宽度:18湿度敏感等级:3
功能数量:1端子数量:165
字数:262144 words字数代码:256000
工作模式:SYNCHRONOUS最高工作温度:70 °C
最低工作温度:组织:256KX18
封装主体材料:PLASTIC/EPOXY封装代码:TBGA
封装形状:RECTANGULAR封装形式:GRID ARRAY, THIN PROFILE
并行/串行:PARALLEL峰值回流温度(摄氏度):260
认证状态:Not Qualified座面最大高度:1.2 mm
最大供电电压 (Vsup):3.465 V最小供电电压 (Vsup):3.135 V
标称供电电压 (Vsup):3.3 V表面贴装:YES
技术:CMOS温度等级:COMMERCIAL
端子面层:TIN SILVER COPPER端子形式:BALL
端子节距:1 mm端子位置:BOTTOM
处于峰值回流温度下的最长时间:30宽度:13 mm
Base Number Matches:1

IDT71V2578YSA150BQG 数据手册

 浏览型号IDT71V2578YSA150BQG的Datasheet PDF文件第2页浏览型号IDT71V2578YSA150BQG的Datasheet PDF文件第3页浏览型号IDT71V2578YSA150BQG的Datasheet PDF文件第4页浏览型号IDT71V2578YSA150BQG的Datasheet PDF文件第5页浏览型号IDT71V2578YSA150BQG的Datasheet PDF文件第6页浏览型号IDT71V2578YSA150BQG的Datasheet PDF文件第7页 
128K X 36, 256K X 18  
IDT71V2576YS  
IDT71V2578YS  
IDT71V2576YSA  
IDT71V2578YSA  
3.3VSynchronousSRAMs  
2.5V I/O, Pipelined Outputs,  
Burst Counter, Single Cycle Deselect  
Features  
Description  
128K x 36, 256K x 18 memory configurations  
The IDT71V2576/78 are high-speed SRAMs organized as 128K x  
36/256Kx18.TheIDT71V2576/78SRAMscontainwrite,data,address  
andcontrolregisters. InternallogicallowstheSRAMtogenerateaself-  
timedwritebaseduponadecisionwhichcanbeleftuntiltheendofthewrite  
cycle.  
Supports high system speed:  
CommercialandIndustrial:  
– 150MHz 3.8ns clock access time  
– 133MHz 4.2ns clock access time  
LBO input selects interleaved or linear burst mode  
Theburstmodefeatureoffersthehighestlevelofperformancetothe  
Self-timedwritecyclewithglobalwritecontrol(GW),bytewrite systemdesigner,astheIDT71V2576/78canprovidefourcyclesofdata  
enable (BWE), and byte writes (BWx)  
3.3V core power supply  
Power down controlled by ZZ input  
2.5V I/O  
Optional - Boundary Scan JTAG Interface (IEEE 1149.1 operationisselected(ADV=LOW),thesubsequentthreecyclesofoutput  
compliant) datawillbeavailabletotheuseronthenextthreerisingclockedges. The  
Packaged in a JEDEC Standard 100-pin plastic thin quad orderofthesethreeaddressesaredefinedbytheinternalburstcounter  
flatpack(TQFP),119ballgridarray(BGA)and165finepitchball andthe LBO inputpin.  
grid array (fBGA)  
forasingleaddress presentedtotheSRAM. Aninternalburstaddress  
counteracceptsthefirstcycleaddressfromtheprocessor,initiatingthe  
accesssequence.Thefirstcycleofoutputdatawillbepipelinedforone  
cycle before it is available on the next rising clock edge. If burst mode  
The IDT71V2576/78 SRAMs utilize IDT’s latest high-performance  
CMOSprocessandarepackagedinaJEDECstandard14mmx20mm  
100-pinthinplasticquadflatpack(TQFP)aswellasa119 ballgridarray  
(BGA) and 165 fine pitch ball grid array (fBGA).  
PinDescriptionSummary  
A0-A17  
Address Inputs  
Input  
Input  
Input  
Input  
Input  
Input  
Input  
Input  
Input  
Input  
Input  
Input  
Input  
Input  
Input  
Output  
Input  
Input  
I/O  
Synchronous  
Synchronous  
Synchronous  
Asynchronous  
Synchronous  
Synchronous  
Synchronous  
N/A  
Chip Enable  
CE  
CS  
0
, CS  
1
Chip Selects  
Output Enable  
OE  
GW  
Global Write Enable  
Byte Write Enable  
Individual Byte Write Selects  
Clock  
BWE  
BW , BW  
(1)  
1
2
, BW  
3
, BW  
4
CLK  
Burst Address Advance  
Address Status (Cache Controller)  
Address Status (Processor)  
Linear / Interleaved Burst Order  
Test Mode Select  
Test Data Input  
Synchronous  
Synchronous  
Synchronous  
DC  
ADV  
ADSC  
ADSP  
LBO  
TMS  
TDI  
Synchronous  
Synchronous  
N/A  
TCK  
TDO  
TRST  
ZZ  
Test Clock  
Test Data Output  
Synchronous  
Asynchronous  
Asynchronous  
Synchronous  
N/A  
JTAG Reset (Optional)  
Sleep Mode  
I/O  
0
-I/O31, I/OP1-I/OP4  
DD, VDDQ  
SS  
Data Input / Output  
Core Power, I/O Power  
Ground  
V
Supply  
Supply  
V
N/A  
6447 tbl 01  
NOTE:  
APRIL 2006  
1. BW3 and BW4 are not applicable for the IDT71V2578.  
1
©2006IntegratedDeviceTechnology,Inc.  
DSC-6447/0A  

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