Datasheet > 存储 > SRAM> IDT71V2578YSA150PFI

IDT71V2578YSA150PFI

更新时间： 2024-11-24 22:08:59

品牌	Logo	应用领域
艾迪悌 - IDT		计数器静态存储器
页数	文件大小	规格书
22页	283K
描述
128K X 36, 256K X 18 3.3V Synchronous SRAMs 2.5V I/O, Pipelined Outputs, Burst Counter, Single Cycle Deselect

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128K X 36, 256K X 18

IDT71V2576S

IDT71V2578S

IDT71V2576SA

IDT71V2578SA

3.3VSynchronousSRAMs

2.5V I/O, Pipelined Outputs,

Burst Counter, Single Cycle Deselect

Features

Description

◆

128K x 36, 256K x 18 memory configurations

The IDT71V2576/78 are high-speed SRAMs organized as 128K x

36/256Kx18.TheIDT71V2576/78SRAMscontainwrite,data,address

andcontrolregisters. InternallogicallowstheSRAMtogenerateaself-

timedwritebaseduponadecisionwhichcanbeleftuntiltheendofthewrite

cycle.

◆

Supports high system speed:

CommercialandIndustrial:

– 150MHz 3.8ns clock access time

– 133MHz 4.2ns clock access time

LBO input selects interleaved or linear burst mode

◆

Theburstmodefeatureoffersthehighestlevelofperformancetothe

◆

Self-timedwritecyclewithglobalwritecontrol(GW),bytewrite systemdesigner,astheIDT71V2576/78canprovidefourcyclesofdata

enable (BWE), and byte writes (BWx)

3.3V core power supply

Power down controlled by ZZ input

2.5V I/O

Optional - Boundary Scan JTAG Interface (IEEE 1149.1 operationisselected(ADV=LOW),thesubsequentthreecyclesofoutput

compliant) datawillbeavailabletotheuseronthenextthreerisingclockedges. The

Packaged in a JEDEC Standard 100-pin plastic thin quad orderofthesethreeaddressesaredefinedbytheinternalburstcounter

flatpack(TQFP),119ballgridarray(BGA)and165finepitchball andthe LBO inputpin.

grid array (fBGA)

forasingleaddress presentedtotheSRAM. Aninternalburstaddress

counteracceptsthefirstcycleaddressfromtheprocessor,initiatingthe

accesssequence.Thefirstcycleofoutputdatawillbepipelinedforone

cycle before it is available on the next rising clock edge. If burst mode

◆

The IDT71V2576/78 SRAMs utilize IDT’s latest high-performance

CMOSprocessandarepackagedinaJEDECstandard14mmx20mm

100-pinthinplasticquadflatpack(TQFP)aswellasa119 ballgridarray

(BGA) and 165 fine pitch ball grid array (fBGA).

PinDescriptionSummary

A⁰-A¹⁷

Address Inputs

Input

Output

Input

I/O

Synchronous

Asynchronous

Synchronous

N/A

Chip Enable

CS⁰, CS¹

Chip Selects

Output Enable

Global Write Enable

Byte Write Enable

Individual Byte Write Selects

Clock

BWE

(1)

BW¹, BW², BW³, BW⁴

CLK

Burst Address Advance

Address Status (Cache Controller)

Address Status (Processor)

Linear / Interleaved Burst Order

Test Mode Select

Test Data Input

Synchronous

ADV

ADSC

ADSP

LBO

TMS

Synchronous

N/A

TDI

TCK

Test Clock

TDO

Test Data Output

Synchronous

Asynchronous

Synchronous

N/A

JTAG Reset (Optional)

Sleep Mode

TRST

I/O⁰-I/O³¹, I/O^P1-I/O^P4

V^DD, V^DDQ

VSS

Data Input / Output

Core Power, I/O Power

Ground

Supply

N/A

4876 tbl 01

NOTE:

JUNE 2003

1. BW3 and BW4 are not applicable for the IDT71V2578.

DSC-4876/09

12 3 4 5 6 7...22

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与IDT71V2578YSA150PFI相关器件

型号	品牌	获取价格	描述	数据表
IDT71V2579	IDT	获取价格	128K x 36, 256K x 18 3.3V Synchronous SRAMs 2.5V I/O, Flow-Through Outputs Burst Counter,
IDT71V257975PF	IDT	获取价格	Standard SRAM, 256KX18, 7.5ns, CMOS, PQFP100
IDT71V257980BG	IDT	获取价格	Standard SRAM, 256KX18, 8ns, CMOS, PBGA119
IDT71V257980BGI	IDT	获取价格	Standard SRAM, 256KX18, 8ns, CMOS, PBGA119
IDT71V257980BQ	IDT	获取价格	Standard SRAM, 256KX18, 8ns, CMOS, PBGA165
IDT71V257985BG	IDT	获取价格	Standard SRAM, 256KX18, 8.5ns, CMOS, PBGA119
IDT71V257985BQ	IDT	获取价格	Standard SRAM, 256KX18, 8.5ns, CMOS, PBGA165
IDT71V2579S	IDT	获取价格	128K x 36,256K x 18 3.3V Synchronous SRAMs 2.5V I/O,Flow-Through Outputs Burst Counter,Sin
IDT71V2579S75BG	IDT	获取价格	128K x 36,256K x 18 3.3V Synchronous SRAMs 2.5V I/O,Flow-Through Outputs Burst Counter,Sin
IDT71V2579S75BGG	IDT	获取价格	Cache SRAM, 256KX18, 7.5ns, CMOS, PBGA119, BGA-119

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