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IDT71V2559S80PFI8 PDF预览

IDT71V2559S80PFI8

更新时间： 2024-09-29 14:51:27
品牌 Logo 应用领域
艾迪悌 - IDT 时钟静态存储器内存集成电路
页数 文件大小 规格书
26页 486K
描述
ZBT SRAM, 256KX18, 8ns, CMOS, PQFP100, 14 X 20 MM, 1.40 MM HEIGHT, PLASTIC, TQFP-100

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IDT71V2559S80PFI8 技术参数

是否Rohs认证：不符合生命周期：Obsolete
零件包装代码：QFP包装说明：14 X 20 MM, 1.40 MM HEIGHT, PLASTIC, TQFP-100
针数：100Reach Compliance Code：not_compliant
ECCN代码：3A991.B.2.AHTS代码：8542.32.00.41
风险等级：5.91Is Samacsys：N
最长访问时间：8 ns其他特性：FLOW-THROUGH ARCHITECTURE
最大时钟频率 (fCLK)：95 MHzI/O 类型：COMMON
JESD-30 代码：R-PQFP-G100JESD-609代码：e0
长度：20 mm内存密度：4718592 bit
内存集成电路类型：ZBT SRAM内存宽度：18
湿度敏感等级：3功能数量：1
端子数量：100字数：262144 words
字数代码：256000工作模式：SYNCHRONOUS
最高工作温度：85 °C最低工作温度：-40 °C
组织：256KX18输出特性：3-STATE
封装主体材料：PLASTIC/EPOXY封装代码：LQFP
封装等效代码：QFP100,.63X.87封装形状：RECTANGULAR
封装形式：FLATPACK, LOW PROFILE并行/串行：PARALLEL
峰值回流温度（摄氏度）：240电源：2.5,3.3 V
认证状态：Not Qualified座面最大高度：1.6 mm
最大待机电流：0.045 A最小待机电流：3.14 V
子类别：SRAMs最大压摆率：0.26 mA
最大供电电压 (Vsup)：3.465 V最小供电电压 (Vsup)：3.135 V
标称供电电压 (Vsup)：3.3 V表面贴装：YES
技术：CMOS温度等级：INDUSTRIAL
端子面层：Tin/Lead (Sn85Pb15)端子形式：GULL WING
端子节距：0.65 mm端子位置：QUAD
处于峰值回流温度下的最长时间：20宽度：14 mm
Base Number Matches：1

IDT71V2559S80PFI8 数据手册

 浏览型号IDT71V2559S80PFI8的Datasheet PDF文件第2页浏览型号IDT71V2559S80PFI8的Datasheet PDF文件第3页浏览型号IDT71V2559S80PFI8的Datasheet PDF文件第4页浏览型号IDT71V2559S80PFI8的Datasheet PDF文件第5页浏览型号IDT71V2559S80PFI8的Datasheet PDF文件第6页浏览型号IDT71V2559S80PFI8的Datasheet PDF文件第7页 
128K x 36, 256K x 18,  
IDT71V2557  
IDT71V2559  
3.3V Synchronous ZBT™SRAMs  
2.5V I/O, Burst Counter,  
Flow-Through Outputs  
Features  
◆
128K x 36, 256K x 18 memory configurations  
The IDT71V2557/59 contain address, data-in and control signal  
registers.Theoutputsareflow-through(nooutputdataregister).Output  
enable is the only asynchronous signal and can be used to disable the  
outputsatanygiventime.  
◆
Supports high performance system speed - 100 MHz  
(7.5 ns Clock-to-Data Access)  
ZBTTM Feature - No dead cycles between write and read  
◆
cycles  
A Clock Enable (CEN) pin allows operation of the IDT71V2557/59  
◆
Internally synchronized output buffer enable eliminates the to be suspended as long as necessary. All synchronous inputs are  
need to control OE  
ignored when (CEN) is high and the internal device registers will hold  
their previous values.  
◆
◆
◆
◆
◆
◆
◆
Single R/W (READ/WRITE) control pin  
4-word burst capability (Interleaved or linear)  
Individual byte write (BW1 - BW4) control (May tie active)  
Three chip enables for simple depth expansion  
3.3V power supply (±5%)  
There are three chip enable pins (CE1, CE2, CE2) that allow the  
usertodeselectthedevicewhendesired.Ifanyoneofthesethreeisnot  
assertedwhenADV/LDislow,nonewmemoryoperationcanbeinitiated.  
However,anypendingdatatransfers(readsorwrites)willbecompleted.  
Thedatabuswilltri-stateonecycleafterthechipisdeselectedorawrite  
isinitiated.  
The IDT71V2557/59 have an on-chip burst counter. In the burst  
mode, the IDT71V2557/59 can provide four cycles of data for a single  
address presented to the SRAM. The order of the burst sequence is  
defined by the LBO input pin. The LBO pin selects between linear and  
interleaved burst sequence. The ADV/LD signal is used to load a new  
external address (ADV/LD = LOW) or increment the internal burst  
counter (ADV/LD = HIGH).  
2.5V (±5%)I/O Supply (VDDQ)  
Packaged in a JEDEC Standard 100-pin plastic thin quad  
flatpack (TQFP), 119 ball grid array (BGA) and 165 fine pitch  
ball grid array (fBGA)  
Description  
TheIDT71V2557/59are3.3Vhigh-speed4,718,592-bit(4.5Mega-  
bit)synchronousSRAMsorganizedas128Kx36/256Kx18.Theyare  
designed to eliminate dead bus cycles when turning the bus around  
between reads and writes, or writes and reads. Thus they have been  
The IDT71V2557/59 SRAMs utilize IDT's latest high-performance  
CMOSprocessandarepackagedinaJEDECstandard14mmx20mm  
100-pin thin plastic quad flatpack (TQFP) as well as a 119 ball  
grid array (BGA) and a 165 fine pitch ball grid array (fBGA).  
TM  
given the name ZBT , or Zero Bus Turnaround.  
AddressandcontrolsignalsareappliedtotheSRAMduringoneclock  
cycle,andonthenextclockcycletheassociateddatacycleoccurs,be  
it read or write.  
PinDescriptionSummary  
0
17  
A -A  
Address Inputs  
Input  
Input  
Input  
Input  
Input  
Input  
Input  
Input  
Input  
I/O  
Synchronous  
Synchronous  
Asynchronous  
Synchronous  
Synchronous  
Synchronous  
N/A  
Chip Enables  
1
2
2
CE , CE , CE  
Output Enable  
OE  
R/W  
CEN  
Read/Write Signal  
Clock Enable  
Individual Byte Write Selects  
Clock  
1
2
3
4
BW , BW , BW , BW  
CLK  
ADV/LD  
LBO  
Advance burst address / Load new address  
Linear / Interleaved Burst Order  
Data Input / Output  
Core Power, I/O Power  
Ground  
Synchronous  
Static  
0
31  
P1  
P4  
I/O -I/O , I/O -I/O  
Synchronous  
Static  
DD DDQ  
V , V  
Supply  
Supply  
SS  
V
Static  
4878 tbl 01  
ZBT and ZeroBus Turnaround are trademarks of Integrated Device Technology, Inc. and the architecture is supported by Micron Technology and Motorola Inc.  
OCTOBER 2000  
1
©2000IntegratedDeviceTechnology,Inc.  
DSC-4878/05  
1234567...26

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与IDT71V2559S80PFI8相关器件

型号 品牌 获取价格 描述 数据表
IDT71V2559S80PFI9 IDT

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 		ZBT SRAM, 256KX18, 8ns, CMOS, PQFP100, PLASTIC, TQFP-100
IDT71V2559S85BG ETC

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 		SYNC SRAM|256KX18|CMOS|BGA|119PIN|PLASTIC
IDT71V2559S85BG8 IDT

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 		ZBT SRAM, 256KX18, 8.5ns, CMOS, PBGA119, 14 X 22 MM, PLASTIC, BGA-119
IDT71V2559S85BGG IDT

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 		ZBT SRAM, 256KX18, 8.5ns, CMOS, PBGA119, 14 X 22 MM, PLASTIC, BGA-119
IDT71V2559S85BGGI IDT

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 		ZBT SRAM, 256KX18, 8.5ns, CMOS, PBGA119, 14 X 22 MM, PLASTIC, BGA-119
IDT71V2559S85BGI8 IDT

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 		ZBT SRAM, 256KX18, 8.5ns, CMOS, PBGA119, 14 X 22 MM, PLASTIC, BGA-119
IDT71V2559S85PF ETC

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 		SYNC SRAM|256KX18|CMOS|QFP|100PIN|PLASTIC
IDT71V2559S85PF9 IDT

获取价格

 		ZBT SRAM, 256KX18, 8.5ns, CMOS, PQFP100, PLASTIC, TQFP-100
IDT71V2559S85PFGI IDT

获取价格

 		ZBT SRAM, 256KX18, 8.5ns, CMOS, PQFP100, 14 X 20 MM, 1.40 MM HEIGHT, PLASTIC, TQFP-100
IDT71V2559S85PFI8 IDT

获取价格

 		ZBT SRAM, 256KX18, 8.5ns, CMOS, PQFP100, 14 X 20 MM, 1.40 MM HEIGHT, PLASTIC, TQFP-100

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