Datasheet > IDT71V2557S75PF

IDT71V2557S75PF

更新时间： 2024-11-15 23:58:11

品牌	Logo	应用领域
其他 - ETC		内存集成电路静态存储器时钟
页数	文件大小	规格书
28页	516K
描述
SYNC SRAM\|128KX36\|CMOS\|QFP\|100PIN\|PLASTIC

阅读下载

中文翻译

获取价格

数据手册

如果您发现信息不准确，欢迎纠错

IDT71V2557S75PF 数据手册

128K x 36, 256K x 18,

IDT71V2557S

IDT71V2559S

IDT71V2557SA

IDT71V2559SA

3.3V Synchronous ZBT™SRAMs

2.5V I/O, Burst Counter,

Flow-Through Outputs

Features

◆

it read or write.

128K x 36, 256K x 18 memory configurations

◆

The IDT71V2557/59 contain address, data-in and control signal

registers.Theoutputsareflow-through(nooutputdataregister).Output

enable is the only asynchronous signal and can be used to disable the

outputsatanygiventime.

A Clock Enable (CEN) pin allows operation of the IDT71V2557/59

to be suspended as long as necessary. All synchronous inputs are

ignored when (CEN) is high and the internal device registers will hold

their previous values.

There are three chip enable pins (CE1, CE2, CE2) that allow the

usertodeselectthedevicewhendesired.Ifanyoneofthesethreeisnot

assertedwhenADV/LDislow,nonewmemoryoperationcanbeinitiated.

However,anypendingdatatransfers(readsorwrites)willbecompleted.

Thedatabuswilltri-stateonecycleafterthechipisdeselectedorawrite

isinitiated.

Supports high performance system speed - 100 MHz

(7.5 ns Clock-to-Data Access)

ZBT^TMFeature - No dead cycles between write and read

◆

cycles

◆

Internally synchronized output buffer enable eliminates the

need to control OE

Single R/W (READ/WRITE) control pin

4-word burst capability (Interleaved or linear)

Individual byte write (BW1 - BW4) control (May tie active)

Three chip enables for simple depth expansion

3.3V power supply (±5%), 2.5V (±5%)I/O Supply (VDDQ)

Optional-Boundary Scan JTAG Interface (IEEE 1149.1

◆

complaint)

◆

Packaged in a JEDEC Standard 100-pin plastic thin quad

The IDT71V2557/59 have an on-chip burst counter. In the burst

mode, the IDT71V2557/59 can provide four cycles of data for a single

address presented to the SRAM. The order of the burst sequence is

defined by the LBO input pin. The LBO pin selects between linear and

interleaved burst sequence. The ADV/LD signal is used to load a new

external address (ADV/LD = LOW) or increment the internal burst

counter (ADV/LD = HIGH).

The IDT71V2557/59 SRAMs utilize IDT's latest high-performance

CMOSprocessandarepackagedinaJEDECstandard14mmx20mm

100-pin thin plastic quad flatpack (TQFP) as well as a 119 ball

grid array (BGA) and a 165 fine pitch ball grid array (fBGA).

flatpack (TQFP), 119 ball grid array (BGA) and 165 fine pitch

ball grid array (fBGA)

Description

TheIDT71V2557/59are3.3Vhigh-speed4,718,592-bit(4.5Mega-

bit)synchronousSRAMsorganizedas128Kx36/256Kx18.Theyare

designed to eliminate dead bus cycles when turning the bus around

between reads and writes, or writes and reads. Thus they have been

given the name ZBT , or Zero Bus Turnaround.

AddressandcontrolsignalsareappliedtotheSRAMduringoneclock

cycle,andonthenextclockcycletheassociateddatacycleoccurs,be

PinDescriptionSummary

A⁰-A¹⁷

Address Inputs

Input

Output

Input

I/O

Synchronous

Asynchronous

Synchronous

N/A

Chip Enables

CE , CE , CE

Output Enable

R/W

CEN

Read/Write Signal

Clock Enable

Individual Byte Write Selects

Clock

BW , BW , BW , BW

CLK

ADV/LD

LBO

Advance burst address / Load new address

Linear / Interleaved Burst Order

Test Mode Select

Test Data Input

Synchronous

Static

TMS

TDI

Synchronous

N/A

TCK

TDO

TRST

Test Clock

Test Data Output

Synchronous

Asynchronous

Synchronous

Static

JTAG Reset (Optional)

Sleep Mode

I/O -I/O , I/O -I/O

Data Input / Output

Core Power, I/O Power

Ground

DD DDQ

, V

Supply

Static

4878 tbl 01

MAY 2002

DSC-4878/06

12 3 4 5 6 7...28

中文翻译

下载PDF

与IDT71V2557S75PF相关器件

型号	品牌	获取价格	描述	数据表
IDT71V2557S75PF8	IDT	获取价格	ZBT SRAM, 128KX36, 7.5ns, CMOS, PQFP100, 14 X 20 MM, 1.40 MM HEIGHT, PLASTIC, TQFP-100
IDT71V2557S75PFG	IDT	获取价格	ZBT SRAM, 128KX36, 7.5ns, CMOS, PQFP100, 14 X 20 MM, 1.40 MM HEIGHT, GREEN, PLASTIC, TQFP-
IDT71V2557S80BG	IDT	获取价格	ZBT SRAM, 128KX36, 8ns, CMOS, PBGA119, 14 X 22 MM, PLASTIC, BGA-119
IDT71V2557S80BG8	IDT	获取价格	ZBT SRAM, 128KX36, 8ns, CMOS, PBGA119, 14 X 22 MM, PLASTIC, BGA-119
IDT71V2557S80BGG	IDT	获取价格	ZBT SRAM, 128KX36, 8ns, CMOS, PBGA119, 14 X 22 MM, PLASTIC, BGA-119
IDT71V2557S80BGGI	IDT	获取价格	ZBT SRAM, 128KX36, 8ns, CMOS, PBGA119, 14 X 22 MM, PLASTIC, BGA-119
IDT71V2557S80BGI8	IDT	获取价格	ZBT SRAM, 128KX36, 8ns, CMOS, PBGA119, 14 X 22 MM, PLASTIC, BGA-119
IDT71V2557S80BQGI	IDT	获取价格	ZBT SRAM, 128KX36, 8ns, CMOS, PBGA165, 13 X 15 MM, FBGA-165
IDT71V2557S80PF	ETC	获取价格	SYNC SRAM\|128KX36\|CMOS\|QFP\|100PIN\|PLASTIC
IDT71V2557S80PF8	IDT	获取价格	ZBT SRAM, 128KX36, 8ns, CMOS, PQFP100, 14 X 20 MM, 1.40 MM HEIGHT, PLASTIC, TQFP-100

与IDT71V2557S75PF相关文章

解析光耦仿真器：升级光耦合器技术的必要性
2024-11-18

13
英伟达新一代Blackwell GPU过热问题致交付延迟
2024-11-18

7
国产厂商思特威CMOS图像传感器芯片单月出货超1亿颗，技术创新引领行业发展
2024-11-14

34
台积电5nm和3nm产能利用率达100%，半导体行业景气度持续攀升
2024-11-14

31

产品中心

服务支持

精选活动

关于我们

帮助中心

IDT71V2557S75PF

IDT71V2557S75PF 数据手册

与IDT71V2557S75PF相关器件

与IDT71V2557S75PF相关文章

您还可以找

产品中心

服务支持

精选活动

关于我们

帮助中心

IDT71V2557S75PF

IDT71V2557S75PF 数据手册

与IDT71V2557S75PF相关器件

与IDT71V2557S75PF相关文章

您还可以找

您在本页遇到什么问题？