Datasheet > IDT71V2557S85PF9

IDT71V2557S85PF9

更新时间： 2024-11-17 04:37:11

品牌	Logo	应用领域
艾迪悌 - IDT		静态存储器
页数	文件大小	规格书
28页	993K
描述
ZBT SRAM, 128KX36, 8.5ns, CMOS, PQFP100, PLASTIC, TQFP-100

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中文翻译

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数据手册

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IDT71V2557S85PF9 数据手册

128K x 36, 256K x 18,

IDT71V2557S

IDT71V2559S

IDT71V2557SA

IDT71V2559SA

3.3V Synchronous ZBT™ SRAMs

2.5V I/O, Burst Counter,

Flow-Through Outputs

Features

◆

it read or write.

128K x 36, 256K x 18 memory configurations

Supports high performance system speed - 100 MHz

(7.5 ns Clock-to-Data Access)

◆

The IDT71V2557/59 contain address, data-in and control signal

registers.Theoutputsareflow-through(nooutputdataregister).Output

enable is the only asynchronous signal and can be used to disable the

outputsatanygiventime.

A Clock Enable (CEN) pin allows operation of the IDT71V2557/59

to be suspended as long as necessary. All synchronous inputs are

ignored when (CEN) is high and the internal device registers will hold

their previous values.

There are three chip enable pins (CE1, CE2, CE2) that allow the

usertodeselectthedevicewhendesired.Ifanyoneofthesethreeisnot

assertedwhenADV/LDislow,nonewmemoryoperationcanbeinitiated.

However,anypendingdatatransfers(readsorwrites)willbecompleted.

Thedatabuswilltri-stateonecycleafterthechipisdeselectedorawrite

isinitiated.

The IDT71V2557/59 have an on-chip burst counter. In the burst

mode, the IDT71V2557/59 can provide four cycles of data for a single

address presented to the SRAM. The order of the burst sequence is

defined by the LBO input pin. The LBO pin selects between linear and

interleaved burst sequence. The ADV/LD signal is used to load a new

external address (ADV/LD = LOW) or increment the internal burst

counter (ADV/LD = HIGH).

ZBT^TMFeature - No dead cycles between write and read

cycles

Internally synchronized output buffer enable eliminates the

need to control OE

Single R/W (READ/WRITE) control pin

4-word burst capability (Interleaved or linear)

Individual byte write (BW¹- BW⁴) control (May tie active)

Three chip enables for simple depth expansion

3.3V power supply (±5%), 2.5V (±5%)I/O Supply (VDDQ)

Optional-Boundary Scan JTAG Interface (IEEE 1149.1

complaint)

Packaged in a JEDEC Standard 100-pin plastic thin quad

flatpack (TQFP), 119 ball grid array (BGA) and 165 fine pitch

ball grid array (fBGA)

◆

Description

TheIDT71V2557/59are3.3Vhigh-speed4,718,592-bit(4.5Mega-

bit)synchronousSRAMsorganizedas128Kx36/256Kx18.Theyare

designed to eliminate dead bus cycles when turning the bus around

between reads and writes, or writes and reads. Thus they have been

given the name ZBT^TM, or Zero Bus Turnaround.

The IDT71V2557/59 SRAMs utilize IDT's latest high-performance

CMOSprocessandarepackagedinaJEDECstandard14mmx20mm

100-pin thin plastic quad flatpack (TQFP) as well as a 119 ball

grid array (BGA) and a 165 fine pitch ball grid array (fBGA).

AddressandcontrolsignalsareappliedtotheSRAMduringoneclock

cycle,andonthenextclockcycletheassociateddatacycleoccurs,be

PinDescriptionSummary

A⁰-A¹⁷

Address Inputs

Input

Output

Input

I/O

Synchronous

Asynchronous

Synchronous

N/A

Chip Enables

CE¹, CE², CE2

Output Enable

R/W

Read/Write Signal

Clock Enable

CEN

Individual Byte Write Selects

Clock

BW¹, BW², BW³, BW4

CLK

ADV/LD

Advance burst address / Load new address

Linear / Interleaved Burst Order

Test Mode Select

Te s t Data Input

Synchronous

Static

LBO

TMS

Synchronous

N/A

TDI

TCK

Te s t Clo c k

TDO

Test Data Output

Synchronous

Asynchronous

Synchronous

Static

JTAG Reset (Optional)

Sleep Mode

TRST

I/O⁰-I/O³¹, I/O^P1-I/O^P4

V^DD, V^DDQ

Data Input / Output

Core Power, I/O Power

Ground

Supply

V^SS

Static

4878 tbl 01

OCTOBER 2004

DSC-4878/07

12 3 4 5 6 7...28

中文翻译

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与IDT71V2557S85PF9相关器件

型号	品牌	获取价格	描述	数据表
IDT71V2557S85PFGI	IDT	获取价格	ZBT SRAM, 128KX36, 8.5ns, CMOS, PQFP100, 14 X 20 MM, 1.40 MM HEIGHT, PLASTIC, TQFP-100
IDT71V2557S85PFI	IDT	获取价格	ZBT SRAM, 128KX36, 8.5ns, CMOS, PQFP100, 14 X 20 MM, 1.40 MM HEIGHT, PLASTIC, TQFP-100
IDT71V2557S85PFI8	IDT	获取价格	ZBT SRAM, 128KX36, 8.5ns, CMOS, PQFP100, 14 X 20 MM, 1.40 MM HEIGHT, PLASTIC, TQFP-100
IDT71V2557S85PFI9	IDT	获取价格	ZBT SRAM, 128KX36, 8.5ns, CMOS, PQFP100, PLASTIC, TQFP-100
IDT71V2558S	IDT	获取价格	128K x 36, 256K x 18 3.3V Synchronous ZBT SRAMs 2.5V I/O, Burst Counter Pipelined Outputs
IDT71V2558S100BG	IDT	获取价格	128K x 36, 256K x 18 3.3V Synchronous ZBT SRAMs 2.5V I/O, Burst Counter Pipelined Outputs
IDT71V2558S100BGG	IDT	获取价格	ZBT SRAM, 256KX18, 5ns, CMOS, PBGA119, 14 X 22 MM, PLASTIC, MS-028AA, BGA-119
IDT71V2558S100BGI	IDT	获取价格	128K x 36, 256K x 18 3.3V Synchronous ZBT SRAMs 2.5V I/O, Burst Counter Pipelined Outputs
IDT71V2558S100BGI8	IDT	获取价格	ZBT SRAM, 256KX18, 5ns, CMOS, PBGA119, 14 X 22 MM, PLASTIC, MS-028AA, BGA-119
IDT71V2558S100BQ	IDT	获取价格	128K x 36, 256K x 18 3.3V Synchronous ZBT SRAMs 2.5V I/O, Burst Counter Pipelined Outputs

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