5秒后页面跳转
捷配首页

Datasheet > IDT71V2557S85PFI9
IDT71V2557S85PFI9 PDF预览

IDT71V2557S85PFI9

更新时间： 2024-09-28 15:42:27
品牌 Logo 应用领域
艾迪悌 - IDT 静态存储器内存集成电路
页数 文件大小 规格书
28页 993K
描述
ZBT SRAM, 128KX36, 8.5ns, CMOS, PQFP100, PLASTIC, TQFP-100

阅读下载

中文翻译

获取价格

IDT71V2557S85PFI9 技术参数

是否Rohs认证： 不符合生命周期：Obsolete
零件包装代码：QFP包装说明：LQFP,
针数：100Reach Compliance Code：compliant
ECCN代码：3A991.B.2.AHTS代码：8542.32.00.41
风险等级：5.92最长访问时间：8.5 ns
其他特性：FLOW-THROUGH ARCHITECTUREJESD-30 代码：R-PQFP-G100
JESD-609代码：e0长度：20 mm
内存密度：4718592 bit内存集成电路类型：ZBT SRAM
内存宽度：36湿度敏感等级：3
功能数量：1端子数量：100
字数：131072 words字数代码：128000
工作模式：SYNCHRONOUS最高工作温度：85 °C
最低工作温度：-40 °C组织：128KX36
封装主体材料：PLASTIC/EPOXY封装代码：LQFP
封装形状：RECTANGULAR封装形式：FLATPACK, LOW PROFILE
并行/串行：PARALLEL峰值回流温度（摄氏度）：240
认证状态：Not Qualified座面最大高度：1.6 mm
最大供电电压 (Vsup)：3.465 V最小供电电压 (Vsup)：3.135 V
标称供电电压 (Vsup)：3.3 V表面贴装：YES
技术：CMOS温度等级：INDUSTRIAL
端子面层：TIN LEAD端子形式：GULL WING
端子节距：0.65 mm端子位置：QUAD
处于峰值回流温度下的最长时间：20宽度：14 mm
Base Number Matches：1

IDT71V2557S85PFI9 数据手册

 浏览型号IDT71V2557S85PFI9的Datasheet PDF文件第2页浏览型号IDT71V2557S85PFI9的Datasheet PDF文件第3页浏览型号IDT71V2557S85PFI9的Datasheet PDF文件第4页浏览型号IDT71V2557S85PFI9的Datasheet PDF文件第5页浏览型号IDT71V2557S85PFI9的Datasheet PDF文件第6页浏览型号IDT71V2557S85PFI9的Datasheet PDF文件第7页 
128K x 36, 256K x 18,  
IDT71V2557S  
IDT71V2559S  
IDT71V2557SA  
IDT71V2559SA  
3.3V Synchronous ZBT™ SRAMs  
2.5V I/O, Burst Counter,  
Flow-Through Outputs  
Features  
◆
it read or write.  
128K x 36, 256K x 18 memory configurations  
Supports high performance system speed - 100 MHz  
(7.5 ns Clock-to-Data Access)  
◆
◆
◆
The IDT71V2557/59 contain address, data-in and control signal  
registers.Theoutputsareflow-through(nooutputdataregister).Output  
enable is the only asynchronous signal and can be used to disable the  
outputsatanygiventime.  
A Clock Enable (CEN) pin allows operation of the IDT71V2557/59  
to be suspended as long as necessary. All synchronous inputs are  
ignored when (CEN) is high and the internal device registers will hold  
their previous values.  
There are three chip enable pins (CE1, CE2, CE2) that allow the  
usertodeselectthedevicewhendesired.Ifanyoneofthesethreeisnot  
assertedwhenADV/LDislow,nonewmemoryoperationcanbeinitiated.  
However,anypendingdatatransfers(readsorwrites)willbecompleted.  
Thedatabuswilltri-stateonecycleafterthechipisdeselectedorawrite  
isinitiated.  
The IDT71V2557/59 have an on-chip burst counter. In the burst  
mode, the IDT71V2557/59 can provide four cycles of data for a single  
address presented to the SRAM. The order of the burst sequence is  
defined by the LBO input pin. The LBO pin selects between linear and  
interleaved burst sequence. The ADV/LD signal is used to load a new  
external address (ADV/LD = LOW) or increment the internal burst  
counter (ADV/LD = HIGH).  
ZBTTM Feature - No dead cycles between write and read  
cycles  
Internally synchronized output buffer enable eliminates the  
need to control OE  
Single R/W (READ/WRITE) control pin  
4-word burst capability (Interleaved or linear)  
Individual byte write (BW1 - BW4) control (May tie active)  
Three chip enables for simple depth expansion  
3.3V power supply (±5%), 2.5V (±5%)I/O Supply (VDDQ)  
Optional-Boundary Scan JTAG Interface (IEEE 1149.1  
complaint)  
Packaged in a JEDEC Standard 100-pin plastic thin quad  
flatpack (TQFP), 119 ball grid array (BGA) and 165 fine pitch  
ball grid array (fBGA)  
◆
◆
◆
◆
◆
◆
◆
Description  
TheIDT71V2557/59are3.3Vhigh-speed4,718,592-bit(4.5Mega-  
bit)synchronousSRAMsorganizedas128Kx36/256Kx18.Theyare  
designed to eliminate dead bus cycles when turning the bus around  
between reads and writes, or writes and reads. Thus they have been  
given the name ZBTTM, or Zero Bus Turnaround.  
The IDT71V2557/59 SRAMs utilize IDT's latest high-performance  
CMOSprocessandarepackagedinaJEDECstandard14mmx20mm  
100-pin thin plastic quad flatpack (TQFP) as well as a 119 ball  
grid array (BGA) and a 165 fine pitch ball grid array (fBGA).  
AddressandcontrolsignalsareappliedtotheSRAMduringoneclock  
cycle,andonthenextclockcycletheassociateddatacycleoccurs,be  
PinDescriptionSummary  
A0-A17  
Address Inputs  
Input  
Input  
Input  
Input  
Input  
Input  
Input  
Input  
Input  
Input  
Input  
Input  
Output  
Input  
Input  
I/O  
Synchronous  
Synchronous  
Asynchronous  
Synchronous  
Synchronous  
Synchronous  
N/A  
Chip Enables  
CE1, CE2, CE2  
Output Enable  
OE  
R/W  
Read/Write Signal  
Clock Enable  
CEN  
Individual Byte Write Selects  
Clock  
BW1, BW2, BW3, BW4  
CLK  
ADV/LD  
Advance burst address / Load new address  
Linear / Interleaved Burst Order  
Test Mode Select  
Te s t Data Input  
Synchronous  
Static  
LBO  
TMS  
Synchronous  
Synchronous  
N/A  
TDI  
TCK  
Te s t Clo c k  
TDO  
Test Data Output  
Synchronous  
Asynchronous  
Synchronous  
Synchronous  
Static  
JTAG Reset (Optional)  
Sleep Mode  
TRST  
ZZ  
I/O0-I/O31, I/OP1-I/OP4  
VDD, VDDQ  
Data Input / Output  
Core Power, I/O Power  
Ground  
Supply  
Supply  
VSS  
Static  
4878 tbl 01  
OCTOBER 2004  
1
©2004IntegratedDeviceTechnology,Inc.  
DSC-4878/07  
1234567...28

中文翻译

下载PDF

与IDT71V2557S85PFI9相关器件

型号 品牌 获取价格 描述 数据表
IDT71V2558S IDT

获取价格

 		128K x 36, 256K x 18 3.3V Synchronous ZBT SRAMs 2.5V I/O, Burst Counter Pipelined Outputs
IDT71V2558S100BG IDT

获取价格

 		128K x 36, 256K x 18 3.3V Synchronous ZBT SRAMs 2.5V I/O, Burst Counter Pipelined Outputs
IDT71V2558S100BGG IDT

获取价格

 		ZBT SRAM, 256KX18, 5ns, CMOS, PBGA119, 14 X 22 MM, PLASTIC, MS-028AA, BGA-119
IDT71V2558S100BGI IDT

获取价格

 		128K x 36, 256K x 18 3.3V Synchronous ZBT SRAMs 2.5V I/O, Burst Counter Pipelined Outputs
IDT71V2558S100BGI8 IDT

获取价格

 		ZBT SRAM, 256KX18, 5ns, CMOS, PBGA119, 14 X 22 MM, PLASTIC, MS-028AA, BGA-119
IDT71V2558S100BQ IDT

获取价格

 		128K x 36, 256K x 18 3.3V Synchronous ZBT SRAMs 2.5V I/O, Burst Counter Pipelined Outputs
IDT71V2558S100BQG IDT

获取价格

 		ZBT SRAM, 256KX18, 5ns, CMOS, PBGA165, 13 X 15 MM, FBGA-165
IDT71V2558S100BQGI IDT

获取价格

 		ZBT SRAM, 256KX18, 5ns, CMOS, PBGA165, 13 X 15 MM, FBGA-165
IDT71V2558S100BQI IDT

获取价格

 		128K x 36, 256K x 18 3.3V Synchronous ZBT SRAMs 2.5V I/O, Burst Counter Pipelined Outputs
IDT71V2558S100PF IDT

获取价格

 		128K x 36, 256K x 18 3.3V Synchronous ZBT SRAMs 2.5V I/O, Burst Counter Pipelined Outputs

与IDT71V2557S85PFI9相关文章

您还可以找


热门产品
PCB打样/小批量
铝基板
BOM智能配单
PCBA制造
钣金
精密CNC
模具注塑
薄膜开关
精选活动
PCBA打样特惠
四六层板品质升级
铝基板品质升级
一体化电子制造
DFM下载
服务支持
企业认证
产品展示
工厂展示
工艺能力
积分商城
关于捷配
捷配简介
企业文化
公司动态
人才招聘
联系我们
帮助中心
下单流程
付款流程
开票流程
常见问题
全球PCB制造服务专线 400-613-0088

工作时间：9:00-21:00

CEO邮箱：ceo@jiepei.com

投诉邮箱：tousu@jiepei.com

捷配网-微信公众号 微信公众号
捷配网-微信公众号 抖音公众号
资质认证：
合作快递：
支付方式：
Copyright © 2024 Jiepei.com Inc. All Rights Reserved. 版权所有:杭州捷配信息科技有限公司 浙公网安备 33010502006866号 浙ICP备10014259号-119 营业执照ICP证