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IDT7140LA20P PDF预览

IDT7140LA20P

更新时间： 2024-11-14 22:57:19
品牌 Logo 应用领域
艾迪悌 - IDT /
页数 文件大小 规格书
14页 219K
描述
HIGH-SPEED 1K x 8 DUAL-PORT STATIC RAM

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中文翻译

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IDT7140LA20P 技术参数

是否Rohs认证： 不符合生命周期：Obsolete
Reach Compliance Code：unknown风险等级：5.92
最长访问时间：20 nsI/O 类型：COMMON
JESD-30 代码：R-PDIP-T48JESD-609代码：e0
内存密度：8192 bit内存集成电路类型：MULTI-PORT SRAM
内存宽度：8端口数量：2
端子数量：48字数：1024 words
字数代码：1000工作模式：ASYNCHRONOUS
最高工作温度：70 °C最低工作温度：
组织：1KX8输出特性：3-STATE
封装主体材料：PLASTIC/EPOXY封装代码：DIP
封装等效代码：DIP48,.6封装形状：RECTANGULAR
封装形式：IN-LINE并行/串行：PARALLEL
电源：5 V认证状态：Not Qualified
最大待机电流：0.0015 A最小待机电流：2 V
子类别：SRAMs最大压摆率：0.2 mA
标称供电电压 (Vsup)：5 V表面贴装：NO
技术：CMOS温度等级：COMMERCIAL
端子面层：Tin/Lead (Sn85Pb15)端子形式：THROUGH-HOLE
端子节距：2.54 mm端子位置：DUAL
Base Number Matches：1

IDT7140LA20P 数据手册

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IDT7130SA/LA  
IDT7140SA/LA  
HIGH-SPEED  
1K x 8 DUAL-PORT  
STATIC RAM  
Integrated Device Technology, Inc.  
FEATURES  
• High-speed access  
—Military: 25/35/55/100ns (max.)  
—Commercial: 25/35/55/100ns (max.)  
—Commercial: 20ns 7130 in PLCC and TQFP  
• Low-power operation  
—IDT7130/IDT7140SA  
—Active: 550mW (typ.)  
—Standby: 5mW (typ.)  
—IDT7130/IDT7140LA  
—Active: 550mW (typ.)  
—Standby: 1mW (typ.)  
• MASTER IDT7130 easily expands data bus width to  
16-or-more-bits using SLAVE IDT7140  
• On-chip port arbitration logic (IDT7130 Only)  
• BUSY output flag on IDT7130; BUSY input on IDT7140  
• Interrupt flags for port-to-port communication  
• Fully asynchronous operation from either port  
• Battery backup operation–2V data retention (LA only)  
• TTL-compatible, single 5V ±10% power supply  
• Military product compliant to MIL-STD-883, Class B  
• Standard Military Drawing #5962-86875  
• Industrial temperature range (–40°C to +85°C) is avail-  
able, tested to military electrical specifications  
DESCRIPTION  
The IDT7130/IDT7140 are high-speed 1K x 8 Dual-Port  
Static RAMs. The IDT7130 is designed to be used as a  
stand-alone 8-bit Dual-Port RAM or as a "MASTER" Dual-  
Port RAM together with the IDT7140 "SLAVE" Dual-Port in  
16-bit-or-more word width systems. Using the IDT MAS-  
TER/SLAVE Dual-Port RAM approach in 16-or-more-bit  
memory system applications results in full-speed, error-free  
operation without the need for additional discrete logic.  
Both devices provide two independent ports with sepa-  
rate control, address, and I/O pins that permit independent  
asynchronous access for reads or writes to any location in  
memory. An automatic power down feature, controlled by  
CE, permits the on chip circuitry of each port to enter a very  
low standby power mode.  
Fabricated using IDT's CMOS high-performance tech-  
nology, these devices typically operate on only 550mW of  
power. Low-power (LA) versions offer battery backup data  
retention capability, with each Dual-Port typically consum-  
ing 200µW from a 2V battery.  
The IDT7130/IDT7140 devices are packaged in 48-pin  
sidebraze or plastic DIPs, LCCs, or flatpacks, 52-pin PLCC,  
and 64-pin TQFP and STQFP. Military grade product is  
manufactured in compliance with the latest revision of MIL-  
STD-883, Class B, making it ideally suited to military tem-  
perature applications demanding the highest level of per-  
formance and reliability.  
FUNCTIONAL BLOCK DIAGRAM  
OER  
OEL  
CEL  
R/WL  
CER  
R/WR  
I/O0L- I/O7L  
I/O0R-I/O7R  
I/O  
Control  
I/O  
Control  
(1,2)  
(1,2)  
BUSYR  
BUSYL  
A9L  
A0L  
A9R  
Address  
Decoder  
MEMORY  
ARRAY  
Address  
Decoder  
A0R  
10  
10  
NOTES:  
ARBITRATION  
and  
INTERRUPT  
LOGIC  
1. IDT7130 (MASTER): BUSY is open  
drain output and requires pullup  
resistor of 270Ω.  
CEL  
OEL  
CER  
OER  
R/WR  
R/WL  
IDT7140 (SLAVE): BUSY is input.  
2. Open drain output: requires pullup  
resistor of 270Ω.  
(2)  
(2)  
INTL  
INTR  
2689 drw 01  
The IDT logo is a registered trademark of Integrated Device Technology, Inc.  
MILITARY AND COMMERCIAL TEMPERATURE RANGES  
OCTOBER 1996  
©1996 Integrated Device Technology, Inc.  
DSC-2689/7  
For latest information contact IDT’s web site at www.idt.com or fax-on-demand at 408-492-8391.  
6.01  
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