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IDT70V9359L9BFI PDF预览

IDT70V9359L9BFI

更新时间: 2024-10-28 22:17:43
品牌 Logo 应用领域
艾迪悌 - IDT /
页数 文件大小 规格书
16页 306K
描述
HIGH-SPEED 3.3V 8/4K x 18 SYNCHRONOUS PIPELINED DUAL-PORT STATIC RAM

IDT70V9359L9BFI 数据手册

 浏览型号IDT70V9359L9BFI的Datasheet PDF文件第2页浏览型号IDT70V9359L9BFI的Datasheet PDF文件第3页浏览型号IDT70V9359L9BFI的Datasheet PDF文件第4页浏览型号IDT70V9359L9BFI的Datasheet PDF文件第5页浏览型号IDT70V9359L9BFI的Datasheet PDF文件第6页浏览型号IDT70V9359L9BFI的Datasheet PDF文件第7页 
IDT70V9359/49L  
HIGH-SPEED 3.3V 8/4K x 18  
SYNCHRONOUS PIPELINED  
DUAL-PORT STATIC RAM  
Features:  
Full synchronous operation on both ports  
– 3.5ns setup to clock and 0ns hold on all control, data, and  
addressinputs  
– Data input, address, and control registers  
– Fast 6.5ns clock to data out in the Pipelined output mode  
– Self-timedwriteallowsfastcycletime  
– 10ns cycle time, 100MHz operation in Pipelined output mode  
Separate upper-byte and lower-byte controls for  
multiplexed bus and bus matching compatibility  
LVTTL- compatible, single 3.3V (±0.3V) power supply  
Industrial temperature range (–40°C to +85°C) is  
available for 83 MHz  
True Dual-Ported memory cells which allow simultaneous  
access of the same memory location  
High-speed clock to data access  
– Commercial:6.5/7.5/9ns(max.)  
– Industrial: 7.5ns (max.)  
Low-power operation  
– IDT70V9359/49L  
Active:450mW(typ.)  
Standby: 1.5mW (typ.)  
Flow-Through or Pipelined output mode on either port via  
the FT/PIPE pins  
Counter enable and reset features  
Dual chip enables allow for depth expansion without  
additional logic  
Available in a 100-pin Thin Quad Flatpack (TQFP) and 100-  
pin Fine Pitch Ball Grid Array (fpBGA) packages.  
FunctionalBlockDiagram  
R/  
W
L
L
R/  
W
R
R
UB  
UB  
CE0L  
CE1L  
CE0R  
CE1R  
1
0
1
0
0/1  
0/1  
LB  
OE  
L
L
LB  
OE  
R
R
1b 0b  
0a 1a  
1a 0a  
0b 1b  
b
FT/PIPE  
L
0/1  
0/1  
b
a
a
FT/PIPE  
R
I/O9L-I/O17L  
I/O0L-I/O8L  
I/O9R-I/O17R  
I/O0R-I/O8R  
(1)  
I/O  
Control  
I/O  
Control  
(1)  
A12L  
A12R  
Counter/  
Address  
Reg.  
Counter/  
Address  
Reg.  
MEMORY  
ARRAY  
A
0R  
CLK  
A
0L  
L
L
R
R
CLK  
ADS  
CNTEN  
CNTRST  
ADS  
CNTEN  
R
L
L
CNTRST  
R
5638 drw 01  
NOTE:  
1. A12 is a NC for IDT70V9349.  
AUGUST 2003  
1
©2003IntegratedDeviceTechnology,Inc.  
DSC-5638/3  

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