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IDT70V9369L12PFI PDF预览

IDT70V9369L12PFI

更新时间: 2024-11-24 22:20:03
品牌 Logo 应用领域
艾迪悌 - IDT /
页数 文件大小 规格书
15页 195K
描述
HIGH-SPEED 3.3V 16K x 18 SYNCHRONOUS PIPELINED DUAL-PORT STATIC RAM

IDT70V9369L12PFI 数据手册

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PRELIMINARY  
IDT70V9369L  
HIGH-SPEED 3.3V 16K x 18  
SYNCHRONOUS PIPELINED  
DUAL-PORT STATIC RAM  
ꢀeatures:  
True Dual-Ported memory cells which allow simultaneous  
access of the same memory location  
High-speed clock to data access  
– Commercial:7.5/9/12ns (max.)  
Industrial:9ns (max.)  
Full synchronous operation on both ports  
4ns setup to clock and 0ns hold on all control, data, and  
addressinputs  
Data input, address, and control registers  
Fast 7.5ns clock to data out in the Pipelined output mode  
Self-timedwriteallowsfastcycletime  
12ns cycle time, 83MHz operation in Pipelined output mode  
Separate upper-byte and lower-byte controls for  
multiplexed bus and bus matching compatibility  
LVTTL- compatible, single 3.3V (±0.3V) power supply  
Industrial temperature range (–40°C to +85°C) is  
available for selected speeds  
Low-power operation  
IDT70V9369L  
Active:500mW(typ.)  
Standby: 1.5mW (typ.)  
Flow-Through or Pipelined output mode on either port via  
the FT/PIPE pins  
Counter enable and reset features  
Dual chip enables allow for depth expansion without  
additional logic  
Available in a 100-pin Thin Quad Flatpack (TQFP)  
ꢀunctionalBlockDiagram  
R/WL  
UBL  
R/WR  
UBR  
CE0L  
CE1L  
CE0R  
CE1R  
1
0
1
0
0/1  
0/1  
LBL  
LBR  
OEL  
OER  
1b 0b  
0a 1a  
0b 1b  
1a 0a  
a
FT/PIPEL  
0/1  
0/1  
b
a
b
FT/PIPER  
I/O9L-I/O17L  
I/O0L-I/O8L  
I/O9R-I/O17R  
I/O0R-I/O8R  
I/O  
Control  
I/O  
Control  
A13R  
A13L  
Counter/  
Address  
Reg.  
Counter/  
Address  
Reg.  
MEMORY  
ARRAY  
A0R  
A0L  
CLKL  
ADSL  
CLKR  
ADSR  
CNTENR  
CNTENL  
CNTRSTL  
CNTRSTR  
5648 drw 01  
JANUARY 2002  
1
©2002IntegratedDeviceTechnology,Inc.  
DSC-5648/1  

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