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IDT70V9379L12PRF8 PDF预览

IDT70V9379L12PRF8

更新时间: 2024-11-25 19:09:23
品牌 Logo 应用领域
艾迪悌 - IDT 静态存储器输出元件内存集成电路
页数 文件大小 规格书
15页 187K
描述
Dual-Port SRAM, 32KX18, 12ns, CMOS, PQFP128, TQFP-128

IDT70V9379L12PRF8 技术参数

是否Rohs认证: 不符合生命周期:Obsolete
零件包装代码:QFP包装说明:TQFP-128
针数:128Reach Compliance Code:not_compliant
ECCN代码:3A991.B.2.BHTS代码:8542.32.00.41
风险等级:5.92最长访问时间:12 ns
其他特性:PIPELINED OUTPUT MODE; SELF-TIMED WRITE CYCLEJESD-30 代码:R-PQFP-G128
JESD-609代码:e0长度:20 mm
内存密度:589824 bit内存集成电路类型:DUAL-PORT SRAM
内存宽度:18湿度敏感等级:3
功能数量:1端子数量:128
字数:32768 words字数代码:32000
工作模式:SYNCHRONOUS最高工作温度:70 °C
最低工作温度:组织:32KX18
封装主体材料:PLASTIC/EPOXY封装代码:LFQFP
封装形状:RECTANGULAR封装形式:FLATPACK, LOW PROFILE, FINE PITCH
并行/串行:PARALLEL峰值回流温度(摄氏度):240
认证状态:Not Qualified座面最大高度:1.6 mm
最大供电电压 (Vsup):3.6 V最小供电电压 (Vsup):3 V
标称供电电压 (Vsup):3.3 V表面贴装:YES
技术:CMOS温度等级:COMMERCIAL
端子面层:TIN LEAD端子形式:GULL WING
端子节距:0.5 mm端子位置:QUAD
处于峰值回流温度下的最长时间:20宽度:14 mm
Base Number Matches:1

IDT70V9379L12PRF8 数据手册

 浏览型号IDT70V9379L12PRF8的Datasheet PDF文件第2页浏览型号IDT70V9379L12PRF8的Datasheet PDF文件第3页浏览型号IDT70V9379L12PRF8的Datasheet PDF文件第4页浏览型号IDT70V9379L12PRF8的Datasheet PDF文件第5页浏览型号IDT70V9379L12PRF8的Datasheet PDF文件第6页浏览型号IDT70V9379L12PRF8的Datasheet PDF文件第7页 
IDT70V9379L  
HIGH-SPEED 3.3V 32K x 18  
SYNCHRONOUS PIPELINED  
DUAL-PORT STATIC RAM  
Features:  
True Dual-Ported memory cells which allow simultaneous  
access of the same memory location  
High-speed clock to data access  
– Commercial:7.5/9/12ns (max.)  
Low-power operation  
Full synchronous operation on both ports  
4ns setup to clock and 0ns hold on all control, data, and  
addressinputs  
Data input, address, and control registers  
Fast 7.5ns clock to data out in the Pipelined output mode  
Self-timedwriteallowsfastcycletime  
IDT70V9379L  
Active:500mW(typ.)  
Standby: 1.5mW (typ.)  
12ns cycle time, 83MHz operation in Pipelined output mode  
Separate upper-byte and lower-byte controls for  
multiplexed bus and bus matching compatibility  
LVTTL- compatible, single 3.3V (±0.3V) power supply  
Industrial temperature range (–40°C to +85°C) is  
available for selected speeds  
Flow-Through or Pipelined output mode on either port via  
the FT/PIPE pins  
Counter enable and reset features  
Dual chip enables allow for depth expansion without  
additional logic  
Available in a 128-pin Thin Quad Flatpack (TQFP)  
FunctionalBlockDiagram  
R/WL  
UBL  
R/WR  
UBR  
CE0L  
CE1L  
CE0R  
CE1R  
1
0
1
0
0/1  
0/1  
LBL  
LBR  
OEL  
OER  
1b 0b  
0a 1a  
0b 1b  
1a 0a  
a
FT/PIPEL  
0/1  
0/1  
b
a
b
FT/PIPER  
I/O9L-I/O17L  
I/O0L-I/O8L  
I/O9R-I/O17R  
I/O0R-I/O8R  
I/O  
Control  
I/O  
Control  
A14R  
A14L  
Counter/  
Address  
Reg.  
Counter/  
Address  
Reg.  
MEMORY  
ARRAY  
A0R  
A0L  
CLKL  
ADSL  
CLKR  
ADSR  
CNTENR  
CNTENL  
CNTRSTL  
CNTRSTR  
4857 drw 01  
JANUARY 2001  
1
©2000IntegratedDeviceTechnology,Inc.  
DSC-4857/2  

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