HIGH-SPEED 3.3V
64K x18/x16
SYNCHRONOUS PIPELINED
DUAL-PORT STATIC RAM
IDT70V9389/289L
Features:
◆
◆
True Dual-Ported memory cells which allow simultaneous
access of the same memory location
High-speed clock to data access
– Commercial:6/7.5/9/12ns(max.)
– Industrial:9ns (max.)
Full synchronous operation on both ports
– 3.5ns setup to clock and 0ns hold on all control, data, and
addressinputs
– Data input, address, and control registers
– Fast 6.5ns clock to data out in the Pipelined output mode
– Self-timedwriteallowsfastcycletime
◆
◆
Low-power operation
– IDT70V9389/289L
– 10ns cycle time, 100MHz operation in Pipelined output mode
Separate upper-byte and lower-byte controls for
multiplexed bus and bus matching compatibility
LVTTL- compatible, single 3.3V (±0.3V) power supply
Industrial temperature range (–40°C to +85°C) is
available for selected speeds
Available in a 128-pin Thin Quad Flatpack (TQFP) and
100-pin Thin Quad Flatpack (TQFP)
Green parts available, see ordering information
◆
Active:500mW(typ.)
Standby: 1.5mW (typ.)
◆
◆
◆
Flow-Through or Pipelined output mode on either port via
the FT/PIPE pins
Counter enable and reset features
Dual chip enables allow for depth expansion without
additional logic
◆
◆
◆
◆
FunctionalBlockDiagram
R/
W
R
R/
W
L
L
UB
R
UB
CE0L
CE1L
CE0R
CE1R
1
0
1
0
0/1
0/1
LB
OE
L
LB
OE
R
L
R
1b 0b
0a 1a
1a 0a
a
0b 1b
b
FT/PIPE
L
0/1
0/1
FT/PIPER
b
a
(1)
(2)
I/O9R-I/O17R
I/O9L-I/O17L
I/O
Control
I/O
Control
(1)
(1)
I/O0R-I/O8R
I/O0L-I/O8L
A
15R
A
15L
0L
L
L
Counter/
Address
Reg.
Counter/
Address
Reg.
A
MEMORY
ARRAY
A
0R
CLK
CLK
ADS
CNTEN
R
R
ADS
CNTEN
R
L
CNTRST
R
CNTRST
L
4856 drw 01
NOTE:
1. I/O0X - I/O7X for IDT70V9289.
2. I/O8X - I/O15X for IDT70V9289.
JUNE 2008
1
©2008IntegratedDeviceTechnology,Inc.
DSC-4856/5