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IDT70V9099L7PFG8 PDF预览

IDT70V9099L7PFG8

更新时间: 2024-10-29 21:00:47
品牌 Logo 应用领域
艾迪悌 - IDT 时钟静态存储器内存集成电路
页数 文件大小 规格书
17页 177K
描述
Application Specific SRAM, 128KX8, 7.5ns, CMOS, PQFP100

IDT70V9099L7PFG8 技术参数

是否无铅: 不含铅是否Rohs认证: 符合
生命周期:ObsoleteReach Compliance Code:unknown
风险等级:5.84最长访问时间:7.5 ns
最大时钟频率 (fCLK):83 MHzI/O 类型:COMMON
JESD-30 代码:S-PQFP-G100JESD-609代码:e3
内存密度:1048576 bit内存集成电路类型:APPLICATION SPECIFIC SRAM
内存宽度:8湿度敏感等级:3
端口数量:2端子数量:100
字数:131072 words字数代码:128000
工作模式:SYNCHRONOUS最低工作温度:
组织:128KX8输出特性:3-STATE
封装主体材料:PLASTIC/EPOXY封装代码:QFP
封装等效代码:QFP100,.63SQ,20封装形状:SQUARE
封装形式:FLATPACK并行/串行:PARALLEL
峰值回流温度(摄氏度):260电源:3.3 V
认证状态:Not Qualified最大待机电流:0.002 A
最小待机电流:3 V子类别:SRAMs
最大压摆率:0.25 mA标称供电电压 (Vsup):3.3 V
表面贴装:YES技术:CMOS
端子面层:Matte Tin (Sn) - annealed端子形式:GULL WING
端子节距:0.5 mm端子位置:QUAD
处于峰值回流温度下的最长时间:30Base Number Matches:1

IDT70V9099L7PFG8 数据手册

 浏览型号IDT70V9099L7PFG8的Datasheet PDF文件第2页浏览型号IDT70V9099L7PFG8的Datasheet PDF文件第3页浏览型号IDT70V9099L7PFG8的Datasheet PDF文件第4页浏览型号IDT70V9099L7PFG8的Datasheet PDF文件第5页浏览型号IDT70V9099L7PFG8的Datasheet PDF文件第6页浏览型号IDT70V9099L7PFG8的Datasheet PDF文件第7页 
HIGH-SPEED 3.3V  
128K x9/x8  
SYNCHRONOUS PIPELINED  
DUAL-PORT STATIC RAM  
IDT70V9199/099L  
Features:  
Counter enable and reset features  
True Dual-Ported memory cells which allow simultaneous  
access of the same memory location  
High-speed clock to data access  
– Commercial:6/7.5/9/12ns(max.)  
Industrial:9ns (max.)  
Full synchronous operation on both ports  
– 3.5ns setup to clock and 0ns hold on all control, data, and  
addressinputs  
Data input, address, and control registers  
– Fast 6.5ns clock to data out in the Pipelined output mode  
– Self-timedwriteallowsfastcycletime  
Low-power operation  
IDT70V9199/099L  
– 10ns cycle time, 100MHz operation in Pipelined output mode  
LVTTL- compatible, single 3.3V (±0.3V) power supply  
Industrial temperature range (–40°C to +85°C) is  
available for selected speeds  
Available in a 100-pin Thin Quad Flatpack (TQFP)  
Green parts available, see ordering information  
Active:500mW(typ.)  
Standby: 1.5mW (typ.)  
Flow-Through or Pipelined output mode on either port via  
the FT/PIPE pins  
Dual chip enables allow for depth expansion without  
additional logic  
FunctionalBlockDiagram  
R/W  
R
R/W  
L
L
OE  
OER  
CE0R  
CE1R  
CE  
CE10LL  
1
0
0/1  
1
0
0/1  
0
1
1
0
0/1  
0/1  
FT/PIPE  
R
FT/PIPE  
L
.
(1)  
(1)  
I/O0R - I/O8R  
I/O0L - I/O8L  
I/O  
Control  
I/O  
Control  
A16L  
A16R  
Counter/  
Address  
Reg.  
Counter/  
Address  
Reg.  
MEMORY  
ARRAY  
A
0L  
A
C0LRK  
R
CLK  
L
L
ADS  
CNTEN  
ADS  
CNTEN  
CNTRST  
R
R
L
R
CNTRST  
L
4859 drw 01  
NOTE:  
1. I/O0X - I/O7X for IDT70V9099.  
JANUARY 2006  
1
©2006IntegratedDeviceTechnology,Inc.  
DSC-4859/4  

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