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IDT70V914S25PFG PDF预览

IDT70V914S25PFG

更新时间: 2024-10-29 14:11:03
品牌 Logo 应用领域
艾迪悌 - IDT 静态存储器内存集成电路
页数 文件大小 规格书
10页 108K
描述
Dual-Port SRAM, 4KX9, 25ns, CMOS, PQFP80, 14 X 14MM, 1.40 MM HEIGHT, TQFP-80

IDT70V914S25PFG 技术参数

是否无铅: 不含铅是否Rohs认证: 符合
生命周期:Obsolete零件包装代码:QFP
包装说明:14 X 14MM, 1.40 MM HEIGHT, TQFP-80针数:80
Reach Compliance Code:compliantECCN代码:EAR99
HTS代码:8542.32.00.41风险等级:5.84
最长访问时间:25 nsJESD-30 代码:S-PQFP-G80
JESD-609代码:e3长度:14 mm
内存密度:36864 bit内存集成电路类型:DUAL-PORT SRAM
内存宽度:9湿度敏感等级:3
功能数量:1端子数量:80
字数:4096 words字数代码:4000
工作模式:SYNCHRONOUS最高工作温度:70 °C
最低工作温度:组织:4KX9
封装主体材料:PLASTIC/EPOXY封装代码:LQFP
封装形状:SQUARE封装形式:FLATPACK, LOW PROFILE
并行/串行:PARALLEL峰值回流温度(摄氏度):260
认证状态:Not Qualified座面最大高度:1.6 mm
最大供电电压 (Vsup):3.6 V最小供电电压 (Vsup):3 V
标称供电电压 (Vsup):3.3 V表面贴装:YES
技术:CMOS温度等级:COMMERCIAL
端子面层:MATTE TIN端子形式:GULL WING
端子节距:0.65 mm端子位置:QUAD
处于峰值回流温度下的最长时间:30宽度:14 mm
Base Number Matches:1

IDT70V914S25PFG 数据手册

 浏览型号IDT70V914S25PFG的Datasheet PDF文件第2页浏览型号IDT70V914S25PFG的Datasheet PDF文件第3页浏览型号IDT70V914S25PFG的Datasheet PDF文件第4页浏览型号IDT70V914S25PFG的Datasheet PDF文件第5页浏览型号IDT70V914S25PFG的Datasheet PDF文件第6页浏览型号IDT70V914S25PFG的Datasheet PDF文件第7页 
IDT70V914S  
HIGH SPEED 3.3V  
(4K X 9) SYNCHRONOUS  
DUAL-PORT RAM  
Features  
High-speed clock-to-data output times  
Data input, address, and control registers  
– Commercial:20/25ns (max.)  
Industrial:20/25ns (max.)  
Low-power operation  
– Fast 20ns clock to data out  
– Self-timedwriteallowsfastcycletimes  
– 20ns cycletimes,50MHzoperation  
LVTTL-compatible, single 3.3V (+ 0.3V) power supply  
Clock Enable feature  
Guaranteed data output hold times  
Available in an 80-pin TQFP  
IDT70V914S  
Active: 250 mW (typ.)  
Standby: 10 mW (typ.)  
Architecture based on Dual-Port RAM cells  
Allowsfullsimultaneousaccessfrombothports  
Synchronous operation  
Industrial temperature range (-40°C to +85°C) is available  
– 5ns setup to clock, 1ns hold on all control, data, and address  
inputs  
FunctionalBlockDiagram  
I/O0-8R  
I/O0-8L  
WRITE  
WRITE  
LOGIC  
MEMORY  
LOGIC  
ARRAY  
SENSE  
AMPS  
SENSE  
AMPS  
DECODER DECODER  
REG  
en  
REG  
en  
OE  
CLK  
CLKEN  
R
OE  
CLK  
CLKEN  
L
L
R
L
R
Self-  
Self-  
timed  
Write  
Logic  
timed  
Write  
Logic  
R/W  
L
REG  
R/WR  
REG  
CEL  
CE  
R
A0R - A11R  
A0L - A11L  
5616 drw 01  
JANUARY 2001  
1
DSC-5616/2  
©2000IntegratedDeviceTechnology,Inc.  

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