IDT70V7339S133DAG

更新时间： 2024-10-29 13:01:27

品牌	Logo	应用领域
艾迪悌 - IDT		/
页数	文件大小	规格书
22页	484K
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IDT70V7339S133DAG 数据手册

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HIGH-SPEED 3.3V 512K x 18

SYNCHRONOUS

BANK-SWITCHABLE

IDT70V7339S

DUAL-PORT STATIC RAM

WITH 3.3V OR 2.5V INTERFACE

Features:

– 1.5ns setup to clock and 0.5ns hold on all control, data, and

address inputs @ 200MHz

◆

512K x 18 Synchronous Bank-Switchable Dual-ported

– Data input, address, byte enable and control registers

– Self-timedwriteallowsfastcycletime

Separate byte controls for multiplexed bus and bus

matching compatibility

LVTTL- compatible, 3.3V (±150mV) power supply

for core

LVTTL compatible, selectable 3.3V (±150mV) or 2.5V

(±100mV) power supply for I/Os and control signals on

each port

Industrial temperature range (-40°C to +85°C) is

available at 166MHz and 133MHz

Available in a 144-pin Thin Quad Flatpack (TQFP),

208-pin fine pitch Ball Grid Array (fpBGA), and 256-pin Ball

GridArray(BGA)

Supports JTAG features compliant with IEEE 1149.1

– Due to limited pin count, JTAG is not supported on the

144-pin TQFP package.

SRAM Architecture

– 64 independent 8K x 18 banks

– 9 megabits of memory on chip

Bank access controlled via bank address pins

High-speed data access

– Commercial:3.4ns (200MHz)/3.6ns (166MHz)/

4.2ns (133MHz) (max.)

– Industrial: 3.6ns (166MHz)/4.2ns (133MHz) (max.)

Selectable Pipelined or Flow-Through output mode

Counter enable and repeat features

Dual chip enables allow for depth expansion without

additional logic

Full synchronous operation on both ports

– 5ns cycle time, 200MHzoperation(14Gbps bandwidth)

– Fast 3.4ns clock to data out

◆

FunctionalBlockDiagram

PL/

OPT^L

CLK^L

PL/FT^R

OPT^R

CLK^R

ADS^L

CNTEN^L

REPEAT^L

R/W^L

ADS^R

CNTEN^R

REPEAT^R

R/W^R

CE^0R

CE^1R

UB^R

LB^R

MUX

CONTROL

LOGIC

CONTROL

LOGIC

CE^0L

CE^1L

UB^L

LB^L

8Kx18

MEMORY

ARRAY

OE^L

OE^R

(BANK 0)

MUX

I/O

CONTROL

I/O

CONTROL

I/O^0L-17L

I/O^0R-17R

8Kx18

MEMORY

ARRAY

A^12R

A^0R

(BANK 1)

A^12L

A^0L

ADDRESS

DECODE

ADDRESS

DECODE

MUX

BA^5R

BA^4R

BA^3R

BA^2R

BA^1R

BA^0R

BA^5L

BA^4L

BANK

DECODE

BANK

DECODE

BA^1L

BA^0L

MUX

8Kx18

MEMORY

ARRAY

(BANK 63)

NOTE:

MUX

JTAG

1. The Bank-Switchable dual-port uses a true SRAM

core instead of the traditional dual-port SRAM core.

As a result, it has unique operating characteristics.

Please refer to the functional description on page 19

for details.

5628 drw 01

TMS

TCK

TDI

TDO

TRST

DECEMBER 2002

DSC 5628/6

12 3 4 5 6 7...22

中文翻译

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与IDT70V7339S133DAG相关器件

型号	品牌	获取价格	描述	数据表
IDT70V7339S133DAGI	IDT	获取价格	Dual-Port SRAM, 512KX18, 15ns, PQFP144, TQFP-144
IDT70V7339S133DAI	IDT	获取价格	Dual-Port SRAM, 512KX18, 15ns, PQFP144, TQFP-144
IDT70V7339S133DD	IDT	获取价格	HIGH-SPEED 3.3V 512K x 18 SYNCHRONOUS BANK-SWITCHABLE DUAL-PORT STATIC RAM WITH 3.3V OR 2.
IDT70V7339S133DDI	IDT	获取价格	HIGH-SPEED 3.3V 512K x 18 SYNCHRONOUS BANK-SWITCHABLE DUAL-PORT STATIC RAM WITH 3.3V OR 2.
IDT70V7339S166BC	IDT	获取价格	HIGH-SPEED 3.3V 512K x 18 SYNCHRONOUS BANK-SWITCHABLE DUAL-PORT STATIC RAM WITH 3.3V OR 2.
IDT70V7339S166BC8	IDT	获取价格	Dual-Port SRAM, 512KX18, 12ns, CMOS, PBGA256, 17 X 17 MM, 1.40 MM HEIGHT, 1 MM PITCH, BGA-
IDT70V7339S166BCG8	IDT	获取价格	Dual-Port SRAM, 512KX18, 12ns, PBGA256, BGA-256
IDT70V7339S166BCGI8	IDT	获取价格	Dual-Port SRAM, 512KX18, 12ns, PBGA256, BGA-256
IDT70V7339S166BCI	IDT	获取价格	HIGH-SPEED 3.3V 512K x 18 SYNCHRONOUS BANK-SWITCHABLE DUAL-PORT STATIC RAM WITH 3.3V OR 2.
IDT70V7339S166BCI8	IDT	获取价格	Dual-Port SRAM, 512KX18, 12ns, CMOS, PBGA256, 17 X 17 MM, 1.40 MM HEIGHT, 1 MM PITCH, BGA-

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