Datasheet > IDT70V7319S200BCI

IDT70V7319S200BCI

更新时间： 2024-10-28 22:08:27

品牌	Logo	应用领域
艾迪悌 - IDT		/
页数	文件大小	规格书
22页	620K
描述
HIGH-SPEED 3.3V 256K x 18 SYNCHRONOUS BANK-SWITCHABLE DUAL-PORT STATIC RAM WITH 3.3V OR 2.5V INTERFACE

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中文翻译

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HIGH-SPEED 3.3V 256K x 18

SYNCHRONOUS

BANK-SWITCHABLE

IDT70V7319S

DUAL-PORT STATIC RAM

WITH 3.3V OR 2.5V INTERFACE

Features:

◆

256K x 18 Synchronous Bank-Switchable Dual-ported

SRAM Architecture

– Data input, address, byte enable and control registers

– Self-timedwriteallowsfastcycletime

Separate byte controls for multiplexed bus and bus

matching compatibility

LVTTL- compatible, 3.3V (±150mV) power supply

for core

LVTTL compatible, selectable 3.3V (±150mV) or 2.5V

(±100mV) power supply for I/Os and control signals on

each port

Industrial temperature range (-40°C to +85°C) is

available at 166MHz and 133MHz

Available in a 144-pin Thin Quad Flatpack (TQFP),

208-pin fine pitch Ball Grid Array (fpBGA), and 256-pin Ball

GridArray(BGA)

Supports JTAG features compliant with IEEE 1149.1

– Due to limited pin count, JTAG is not supported on the

144-pin TQFP package.

◆

– 64 independent 4K x 18 banks

– 4 megabits of memory on chip

Bank access controlled via bank address pins

High-speed data access

◆

– Commercial:3.4ns (200MHz)/3.6ns (166MHz)/

4.2ns (133MHz) (max.)

– Industrial: 3.6ns (166MHz)/4.2ns (133MHz) (max.)

Selectable Pipelined or Flow-Through output mode

Counter enable and repeat features

Dual chip enables allow for depth expansion without

additional logic

Full synchronous operation on both ports

– 5ns cycle time, 200MHzoperation(14Gbps bandwidth)

– Fast 3.4ns clock to data out

◆

– 1.5ns setup to clock and 0.5ns hold on all control, data, and

address inputs @ 200MHz

FunctionalBlockDiagram

PL/FT

OPT

CLK

ADS

CNTEN

REPEAT

R/W

OPT

CLK

ADS

CNTEN

REPEAT

R/W

CE0L

CE1L

MUX

CONTROL

LOGIC

CONTROL

LOGIC

CE0R

CE1R

4Kx18

MEMORY

ARRAY

(BANK 0)

MUX

I/O

CONTROL

I/O

CONTROL

I/O0L-17L

I/O0R-17R

4Kx18

MEMORY

ARRAY

11R

(BANK 1)

11L

ADDRESS

DECODE

ADDRESS

DECODE

MUX

BA5R

BA4R

BA3R

BA2R

BA1R

BA0R

BA5L

BA4L

BA3L

BA2L

BA1L

BA0L

BANK

DECODE

BANK

DECODE

MUX

4Kx18

MEMORY

ARRAY

(BANK 63)

NOTE:

MUX

1. The Bank-Switchable dual-port uses a true SRAM

core instead of the traditional dual-port SRAM core.

As a result, it has unique operating characteristics.

Please refer to the functional description on page 19

for details.

5629 drw 01

TMS

TCK

TRST

TDI

TDO

JTAG

DECEMBER 2002

DSC 5629/6

12 3 4 5 6 7...22

中文翻译

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与IDT70V7319S200BCI相关器件

型号	品牌	获取价格	描述	数据表
IDT70V7319S200BF	IDT	获取价格	HIGH-SPEED 3.3V 256K x 18 SYNCHRONOUS BANK-SWITCHABLE DUAL-PORT STATIC RAM WITH 3.3V OR 2.
IDT70V7319S200BFI	IDT	获取价格	HIGH-SPEED 3.3V 256K x 18 SYNCHRONOUS BANK-SWITCHABLE DUAL-PORT STATIC RAM WITH 3.3V OR 2.
IDT70V7319S200DD	IDT	获取价格	HIGH-SPEED 3.3V 256K x 18 SYNCHRONOUS BANK-SWITCHABLE DUAL-PORT STATIC RAM WITH 3.3V OR 2.
IDT70V7319S200DDI	IDT	获取价格	HIGH-SPEED 3.3V 256K x 18 SYNCHRONOUS BANK-SWITCHABLE DUAL-PORT STATIC RAM WITH 3.3V OR 2.
IDT70V7339S	IDT	获取价格	HIGH-SPEED 3.3V 512K x 18 SYNCHRONOUS BANK-SWITCHABLE DUAL-PORT STATIC RAM WITH 3.3V OR 2.
IDT70V7339S133BC	IDT	获取价格	HIGH-SPEED 3.3V 512K x 18 SYNCHRONOUS BANK-SWITCHABLE DUAL-PORT STATIC RAM WITH 3.3V OR 2.
IDT70V7339S133BC8	IDT	获取价格	Dual-Port SRAM, 512KX18, 15ns, CMOS, PBGA256, 17 X 17 MM, 1.40 MM HEIGHT, 1 MM PITCH, BGA-
IDT70V7339S133BCG	IDT	获取价格	暂无描述
IDT70V7339S133BCG8	IDT	获取价格	Dual-Port SRAM, 512KX18, 15ns, PBGA256, BGA-256
IDT70V7339S133BCI	IDT	获取价格	HIGH-SPEED 3.3V 512K x 18 SYNCHRONOUS BANK-SWITCHABLE DUAL-PORT STATIC RAM WITH 3.3V OR 2.

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