IDT70V657S15DRG

更新时间： 2024-10-29 13:00:23

品牌	Logo	应用领域
艾迪悌 - IDT		/
页数	文件大小	规格书
24页	315K
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中文翻译

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数据手册

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IDT70V657S15DRG 数据手册

HIGH-SPEED 3.3V

128/64/32K x 36

IDT70V659/58/57S

ASYNCHRONOUS DUAL-PORT

STATIC RAM

Features

◆

True Dual-Port memory cells which allow simultaneous

Full on-chip hardware support of semaphore signaling

between ports

Fully asynchronous operation from either port

Separate byte controls for multiplexed bus and bus

matching compatibility

Supports JTAG features compliant to IEEE 1149.1

LVTTL-compatible, single 3.3V (±150mV) power supply for

core

access of the same memory location

High-speed access

◆

– Commercial:10/12/15ns(max.)

– Industrial: 12/15ns(max.)

Dual chip enables allow for depth expansion without

◆

external logic

◆

IDT70V659/58/57 easily expands data bus width to 72 bits

◆

or more using the Master/Slave select when cascading

more than one device

M/S = VIH for BUSY output flag on Master,

M/S = VIL for BUSY input on Slave

Busy and Interrupt Flags

LVTTL-compatible, selectable 3.3V (±150mV)/2.5V (±100mV)

power supply for I/Os and control signals on each port

Available in a 208-pin Plastic Quad Flatpack, 208-ball fine

pitch Ball Grid Array, and 256-ball Ball Grid Array

Industrial temperature range (–40°C to +85°C) is available

for selected speeds

◆

On-chip port arbitration logic

Functional Block Diagram

BE3L

BE3R

BE2R

BE2L

BE1L

BE0L

BE1R

BE0R

R/WL

R/WR

B B B B B B B B

E E E E E E E E

1 0

CE0L

CE1L

CE0R

CE1R

R R R R

OEL

OER

Dout0-8_L

Dout9-17_L

Dout18-26_L

Dout27-35_L

Dout0-8_R

Dout9-17_R

Dout18-26_R

Dout27-35_R

128/64/32K x 36

MEMORY

ARRAY

I/O0L- I/O35L

Di n_L

Di n_R

I/O0R -I/O35R

(1)

16R

(1)

Address

Decoder

16 L

Address

Decoder

ADDR_L

ADDR_R

A0R

A0L

CE0L

CE1L

ARBITRATION

CE0R

CE1R

INTERRUPT

SEMAPHORE

LOGIC

R/W

(2,3)

BUSY

SEM

BUSY

SEM

M/S

(3)

INTL

INT

TMS

TCK

TDI

JTAG

TDO

TRST

NOTES:

4869 drw 01

1. A16 is a NC for IDT70V658. Also, Addresses A16 and A15 are NC's for IDT70V657.

2. BUSY is an input as a Slave (M/S=VIL) and an output when it is a Master (M/S=VIH).

3. BUSY and INT are non-tri-state totem-pole outputs (push-pull).

MARCH 2004

DSC-4869/5

12 3 4 5 6 7...24

中文翻译

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与IDT70V657S15DRG相关器件

型号	品牌	获取价格	描述	数据表
IDT70V657S15DRI	IDT	获取价格	HIGH-SPEED 3.3V 128/64/32K x 36 ASYNCHRONOUS DUAL-PORT STATIC RAM
IDT70V658	IDT	获取价格	HIGH-SPEED 3.3V 64K X 36 ASYNCHRONOUS DUAL-PORT STATIC RAM
IDT70V658S	IDT	获取价格	HIGH-SPEED 3.3V 64K X 36 ASYNCHRONOUS DUAL-PORT STATIC RAM
IDT70V658S10BC	IDT	获取价格	HIGH-SPEED 3.3V 64K X 36 ASYNCHRONOUS DUAL-PORT STATIC RAM
IDT70V658S10BC8	IDT	获取价格	Dual-Port SRAM, 64KX36, 10ns, CMOS, PBGA256, 17 X 17 MM, 1.40 MM HEIGHT, 1 MM PITCH, BGA-2
IDT70V658S10BCI	IDT	获取价格	HIGH-SPEED 3.3V 64K X 36 ASYNCHRONOUS DUAL-PORT STATIC RAM
IDT70V658S10BF	IDT	获取价格	HIGH-SPEED 3.3V 64K X 36 ASYNCHRONOUS DUAL-PORT STATIC RAM
IDT70V658S10BF8	IDT	获取价格	Dual-Port SRAM, 64KX36, 10ns, CMOS, PBGA208, 15 X 15 MM, 1.40 MM HEIGHT, 0.80 MM PITCH, FP
IDT70V658S10BFG	IDT	获取价格	Dual-Port SRAM, 64KX36, 10ns, CMOS, PBGA208, 15 X 15 MM, 1.40 MM HEIGHT, 0.80 MM PITCH, GR
IDT70V658S10BFG8	IDT	获取价格	Dual-Port SRAM, 64KX36, 10ns, CMOS, PBGA208, 15 X 15 MM, 1.40 MM HEIGHT, 0.80 MM PITCH, GR

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