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IDT70V658S12DR PDF预览

IDT70V658S12DR

更新时间: 2024-10-28 23:01:07
品牌 Logo 应用领域
艾迪悌 - IDT /
页数 文件大小 规格书
23页 196K
描述
HIGH-SPEED 3.3V 64K X 36 ASYNCHRONOUS DUAL-PORT STATIC RAM

IDT70V658S12DR 数据手册

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PRELIMINARY  
IDT70V658S  
HIGH-SPEED 3.3V 64K x 36  
ASYNCHRONOUS DUAL-PORT  
STATIC RAM  
Features  
True Dual-Port memory cells which allow simultaneous  
Full on-chip hardware support of semaphore signaling  
between ports  
Fully asynchronous operation from either port  
Separate byte controls for multiplexed bus and bus  
matching compatibility  
Supports JTAG features compliant to IEEE 1149.1  
LVTTL-compatible, single 3.3V (±150mV) power supply  
for core  
access of the same memory location  
High-speed access  
– Commercial:10/12/15ns (max.)  
Industrial:12/15ns (max.)  
Dual chip enables allow for depth expansion without  
external logic  
IDT70V658 easily expands data bus width to 72 bits or  
more using the Master/Slave select when cascading more  
than one device  
M/S = VIH for BUSY output flag on Master,  
M/S = VIL for BUSY input on Slave  
Busy and Interrupt Flags  
LVTTL-compatible, selectable 3.3V (±150mV)/2.5V (±100mV)  
power supply for I/Os and control signals on each port  
Available in 208-pin Plastic Quad Flatpack, 208-ball fine  
pitch Ball Grid Array, and 256-ball Ball Grid Array  
Industrial temperature range (–40°C to +85°C) is available  
for selected speeds  
On-chip port arbitration logic  
Functional Block Diagram  
3
BE  
L
BE  
3
2
R
R
BE  
2
L
BE  
BE  
BE  
1
BE  
BE  
1
0
R
L
L
0
R
R/W  
R/  
W
R
L
B
E
0
L
B
E
1
L
B
E
2
L
B
E
3
L
B
E
3
B
E
2
B
E
1
B
E
0
CE0  
CE  
0
R
R R  
R
L
R
CE1  
R
CE1  
L
OE  
OE  
R
L
Dout0-8_L  
Dout0-8_R  
Dout9-17_L  
Dout9-17_R  
Dout18-26_R  
Dout27-35_R  
Dout18-26_L  
Dout27-35_L  
64K x 36  
MEMORY  
ARRAY  
I/O - I/O  
0L 35L  
Di n_L  
Di n_R  
I/O - I/O  
0R 35R  
A
A
15R  
0R  
A15 L  
A0 L  
Address  
Decoder  
Address  
Decoder  
ADDR_L  
ADDR_R  
CE  
CE1  
0
CE  
0
L
R
ARBITRATION  
R
CE1  
INTERRUPT  
SEMAPHORE  
LOGIC  
L
OE  
OE  
R
L
R/W  
L
R/W  
R
BUSY  
SEM  
BUSY  
R
L
SEM  
M/S  
L
R
INT  
INT  
L
R
TMS  
TCK  
TDI  
JTAG  
TDO  
TRST  
5613 drw 01  
NOTES:  
1. BUSY is an input as a Slave (M/S=VIL) and an output when it is a Master (M/S=VIH).  
2. BUSY and INT are non-tri-state totem-pole outputs (push-pull).  
JUNE 2001  
1
DSC-5613/3  
©2001IntegratedDeviceTechnology,Inc.  

IDT70V658S12DR 替代型号

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