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IDT70V639S10BFI PDF预览

IDT70V639S10BFI

更新时间: 2024-10-27 23:01:07
品牌 Logo 应用领域
艾迪悌 - IDT /
页数 文件大小 规格书
23页 187K
描述
HIGH-SPEED 3.3V 128K x 18 ASYNCHRONOUS DUAL-PORT STATIC RAM

IDT70V639S10BFI 数据手册

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PRELIMINARY  
IDT70V639S  
HIGH-SPEED 3.3V 128K x 18  
ASYNCHRONOUS DUAL-PORT  
STATIC RAM  
Features  
True Dual-Port memory cells which allow simultaneous  
access of the same memory location  
High-speed access  
Fully asynchronous operation from either port  
Separate byte controls for multiplexed bus and bus  
matching compatibility  
Supports JTAG features compliant to IEEE 1149.1  
Due to limited pin count, JTAG is not supported on the  
128-pin TQFP package.  
– Commercial:10/12/15ns (max.)  
Industrial:12/15ns (max.)  
Dual chip enables allow for depth expansion without  
external logic  
IDT70V639 easily expands data bus width to 36 bits or  
more using the Master/Slave select when cascading more  
than one device  
M/S = VIH for BUSY output flag on Master,  
M/S = VIL for BUSY input on Slave  
Busy and Interrupt Flags  
LVTTL-compatible, single 3.3V (±150mV) power supply for  
core  
LVTTL-compatible, selectable 3.3V (±150mV)/2.5V (±100mV)  
power supply for I/Os and control signals on each port  
Available in a 128-pin Thin Quad Flatpack, 208-ball fine  
pitch Ball Grid Array, and 256-ball Ball Grid Array  
Industrial temperature range (–40°C to +85°C) is available  
for selected speeds  
On-chip port arbitration logic  
Full on-chip hardware support of semaphore signaling  
between ports  
Functional Block Diagram  
UB  
L
L
R
UB  
LB  
LB  
R
W
L
R/  
R/  
WR  
B
B
E
1
L
B
E
1
B
E
0
E
0
L
CE0L  
CE0R  
R
R
CE1L  
CE1R  
OEL  
OER  
Dout0-8_L  
Dout9-17_L  
Dout0-8_R  
Dout9-17_R  
128K x 18  
MEMORY  
ARRAY  
Din_L  
I/O0L- I/O17L  
Din_R  
I/O0R - I/O17R  
16R  
0R  
A
16L  
0L  
Address  
Decoder  
Address  
Decoder  
A
ADDR_L  
ADDR_R  
A
A
OE  
L
OER  
ARBITRATION  
INTERRUPT  
SEMAPHORE  
LOGIC  
0R  
CE  
0L  
1L  
CE  
CE  
1R  
CE  
R/  
W
L
R/  
WR  
BUSY  
SEM  
INT  
R
BUSY  
SEM  
INT  
L
L
M/  
S
R
L
R
TMS  
TCK  
TDI  
JTAG  
TDO  
TRST  
5621 drw 01  
NOTES:  
1. BUSY is an input as a Slave (M/S=VIL) and an output when it is a Master (M/S=VIH).  
2. BUSY and INT are non-tri-state totem-pole outputs (push-pull).  
JUNE 2001  
1
DSC-5621/3  
©2001IntegratedDeviceTechnology,Inc.  

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