HIGH-SPEED 3.3V
8/4K x 18 DUAL-PORT
8/4K x 16 DUAL-PORT
STATIC RAM
IDT70V35/34S/L
IDT70V25/24S/L
◆
Features
Separate upper-byte and lower-byte control for multiplexed
bus compatibility
IDT70V35/34 (IDT70V25/24) easily expands data bus width
to 36 bits (32 bits) or more using the Master/Slave select
when cascading more than one device
M/S = VIH for BUSY output flag on Master
M/S = VIL for BUSY input on Slave
BUSY and Interrupt Flag
On-chip port arbitration logic
Full on-chip hardware support of semaphore signaling
between ports
Fully asynchronous operation from either port
LVTTL-compatible, single 3.3V (±0.3V) power supply
Available in a 100-pin TQFP (IDT70V35/24) & (IDT70V25/24),
86-pin PGA (IDT70V25/24) and 84-pin PLCC (IDT70V25/24)
Industrial temperature range (-40°C to +85°C) is available
for selected speeds
◆
True Dual-Ported memory cells which allow simultaneous
◆
◆
reads of the same memory location
High-speed access
◆
IDT70V35/34
– Commercial:15/20/25ns (max.)
– Industrial:20ns
◆
◆
◆
IDT70V25/24
– Commercial:15/20/25/35/55ns(max.)
– Industrial:20/25ns
Low-power operation
◆
◆
◆
◆
– IDT70V35/34S
– IDT70V35/34L
Active: 430mW (typ.)
Standby: 3.3mW (typ.)
Active: 415mW (typ.)
Standby: 660µW (typ.)
◆
– IDT70V25/24S
–
IDT70V25/24L
Active: 400mW (typ.)
Standby: 3.3mW (typ.)
Active: 380mW (typ.)
Standby: 660µW (typ.)
Functional Block Diagram
R/W
L
R/W
R
R
UBL
UB
LB
CE
OE
R
LB
CE
OE
L
R
R
L
L
,
(5)
(5)
I/O9R-I/O17R
I/O9L-I/O17L
I/O
Control
I/O
Control
(4)
(4)
I/O0R-I/O8R
I/O0L-I/O8L
(2,3)
L
(2,3)
BUSY
R
BUSY
(1)
12R
(1)
12L
A
A
Address
Decoder
MEMORY
ARRAY
Address
Decoder
A0L
A
0R
13
13
ARBITRATION
INTERRUPT
SEMAPHORE
LOGIC
CE
OE
R/W
R
CE
OE
L
L
R
R
R/W
L
SEM
R
SEM
INTL
L
(3)
(3)
INTR
M/S
5624 drw 01
NOTES:
1. A12 is a NC for IDT70V34 and for IDT70V24.
2. (MASTER): BUSY is output; (SLAVE): BUSY is input.
3. BUSY outputs and INT outputs are non-tri-stated push-pull.
4. I/O0x - I/O7x for IDT70V25/24.
5. I/O8x - I/O15x for IDT70V25/24.
OCTOBER 2004
1
DSC-5624/5
©2004IntegratedDeviceTechnology,Inc.