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IDT70V261S25PFG PDF预览

IDT70V261S25PFG

更新时间: 2024-11-07 12:58:51
品牌 Logo 应用领域
艾迪悌 - IDT 存储内存集成电路静态存储器
页数 文件大小 规格书
17页 154K
描述
Dual-Port SRAM, 16KX16, 25ns, CMOS, PQFP100, PLASTIC, TQFP-100

IDT70V261S25PFG 技术参数

是否无铅:不含铅是否Rohs认证:符合
生命周期:Active零件包装代码:QFP
包装说明:LFQFP, QFP100,.63SQ,20针数:100
Reach Compliance Code:compliantECCN代码:EAR99
HTS代码:8542.32.00.41风险等级:5.24
Is Samacsys:N最长访问时间:25 ns
其他特性:INTERRUPT FLAG; SEMAPHORE; AUTOMATIC POWER-DOWNI/O 类型:COMMON
JESD-30 代码:S-PQFP-G100JESD-609代码:e3
长度:14 mm内存密度:262144 bit
内存集成电路类型:DUAL-PORT SRAM内存宽度:16
湿度敏感等级:3功能数量:1
端口数量:2端子数量:100
字数:16384 words字数代码:16000
工作模式:ASYNCHRONOUS最高工作温度:70 °C
最低工作温度:组织:16KX16
输出特性:3-STATE可输出:YES
封装主体材料:PLASTIC/EPOXY封装代码:LFQFP
封装等效代码:QFP100,.63SQ,20封装形状:SQUARE
封装形式:FLATPACK, LOW PROFILE, FINE PITCH并行/串行:PARALLEL
峰值回流温度(摄氏度):260电源:3.3 V
认证状态:Not Qualified座面最大高度:1.6 mm
最大待机电流:0.006 A最小待机电流:3 V
子类别:SRAMs最大压摆率:0.17 mA
最大供电电压 (Vsup):3.6 V最小供电电压 (Vsup):3 V
标称供电电压 (Vsup):3.3 V表面贴装:YES
技术:CMOS温度等级:COMMERCIAL
端子面层:Matte Tin (Sn) - annealed端子形式:GULL WING
端子节距:0.5 mm端子位置:QUAD
处于峰值回流温度下的最长时间:30宽度:14 mm
Base Number Matches:1

IDT70V261S25PFG 数据手册

 浏览型号IDT70V261S25PFG的Datasheet PDF文件第2页浏览型号IDT70V261S25PFG的Datasheet PDF文件第3页浏览型号IDT70V261S25PFG的Datasheet PDF文件第4页浏览型号IDT70V261S25PFG的Datasheet PDF文件第5页浏览型号IDT70V261S25PFG的Datasheet PDF文件第6页浏览型号IDT70V261S25PFG的Datasheet PDF文件第7页 
HIGH-SPEED 3.3V  
16K x 16 DUAL-PORT  
STATIC RAM  
IDT70V261S/L  
bus compatibility  
ꢀeatures  
IDT70V261 easily expands data bus width to 32 bits or more  
using the Master/Slave select when cascading more than  
one device  
M/S = VIH for BUSY output flag on Master  
M/S = VIL for BUSY input on Slave  
Interrupt Flag  
On-chip port arbitration logic  
Full on-chip hardware support of semaphore signaling  
between ports  
Fully asynchronous operation from either port  
TTL-compatible, single 3.3V (±0.3V) power supply  
Available in a 100-pin TQFP, Thin Quad Plastic Flatpack  
Industrial temperature range (-40°C to +85°C) is available  
for selected speed  
True Dual-Ported memory cells which allow simultaneous  
access of the same memory location  
High-speed access  
– Commercial:25/35/55ns (max.)  
Industrial:25ns (max.)  
Low-power operation  
IDT70V261S  
Active: 300mW (typ.)  
Standby: 3.3mW (typ.)  
IDT70V261L  
Active: 300mW (typ.)  
Standby: 660µW (typ.)  
Separate upper-byte and lower-byte control for multiplexed  
ꢀunctional Block Diagram  
R/  
UBL  
L
W
R/  
R
UBR  
W
LBL  
CEL  
OEL  
LBR  
CER  
OER  
I/O8L-I/O15L  
I/O8R-I/O15R  
I/O0R-I/O7R  
I/O  
Control  
I/O  
Control  
I/O0L-I/O7L  
(1,2)  
(1,2)  
BUSYL  
BUSYR  
A13R  
A0R  
A13L  
A0L  
Address  
Decoder  
MEMORY  
ARRAY  
Address  
Decoder  
14  
14  
ARBITRATION  
INTERRUPT  
SEMAPHORE  
LOGIC  
CER  
OER  
R/W  
R
CEL  
OEL  
R/  
W
L
SEMR  
INTR  
SEML  
INTL  
(2)  
(2)  
M/  
S
3040 drw 01  
NOTES:  
1. (MASTER): BUSY is output; (SLAVE): BUSY is input.  
2. BUSY and INT outputs are non-tri-stated push-pull.  
DECEMBER 2001  
1
DSC-3040/8  
©2001IntegratedDeviceTechnology,Inc.  

IDT70V261S25PFG 替代型号

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