Datasheet > IDT70T9359L12BF

IDT70T9359L12BF

更新时间： 2024-10-29 03:03:27

品牌	Logo	应用领域
艾迪悌 - IDT		/
页数	文件大小	规格书
16页	203K
描述
HIGH-SPEED 2.5V 8/4K x 18 SYNCHRONOUS PIPELINED DUAL-PORT STATIC RAM

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中文翻译

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数据手册

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IDT70T9359L12BF 数据手册

PRELIMINARY

IDT70T9359/49L

HIGH-SPEED 2.5V 8/4K x 18

SYNCHRONOUS PIPELINED

DUAL-PORT STATIC RAM

◆

ꢀeatures:

Full synchronous operation on both ports

– 4.0ns setup to clock and 0.5ns hold on all control, data, and

addressinputs

– Data input, address, and control registers

– Fast 7.5ns clock to data out in the Pipelined output mode

– Self-timedwriteallowsfastcycletime

– 12ns cycle time, 83MHz operation in Pipelined output mode

Separate upper-byte and lower-byte controls for

multiplexed bus and bus matching compatibility

LVTTL- compatible, single 2.5V (±100mV) power supply

Industrial temperature range (–40°C to +85°C) is

available for 66MHz

◆

True Dual-Ported memory cells which allow simultaneous

access of the same memory location

High-speed clock to data access

– Commercial:7.5/9/12ns(max.)

– Industrial:9ns (max.)

◆

Low-power operation

◆

– IDT70T9359/49L

Active:225mW(typ.)

◆

Standby: 1.5mW (typ.)

Flow-Through or Pipelined output mode on either port via

the FT/PIPE pins

Counter enable and reset features

Dual chip enables allow for depth expansion without

additional logic

◆

Available in a 100-pin Thin Quad Flatpack (TQFP) and 100-

pin fine pitch Ball Grid Array (fpBGA) packages.

ꢀunctionalBlockDiagram

R/WL

UBL

R/WR

UBR

CE0L

CE1L

CE0R

CE1R

0/1

LBL

LBR

OEL

OER

1b 0b

0a 1a

0b 1b

1a 0a

FT/PIPEL

0/1

FT/PIPER

I/O9L-I/O17L

I/O0L-I/O8L

I/O9R-I/O17R

I/O0R-I/O8R

I/O

Control

I/O

Control

(1)

A12L

A12R

Counter/

Address

Reg.

Counter/

Address

Reg.

MEMORY

ARRAY

A0R

A0L

CLKL

ADSL

CLKR

ADSR

CNTENR

CNTENL

CNTRSTL

CNTRSTR

5640 drw 01

NOTE:

1. A¹²is a NC for IDT70T9349.

JULY 2002

DSC-5640/1

12 3 4 5 6 7...16

中文翻译

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IDT70T9359L7PFG	IDT	获取价格	Dual-Port SRAM, 8KX18, 18ns, CMOS, PQFP100, TQFP-100