Datasheet > 存储 > SRAM> IDT70V05L15J

IDT70V05L15J

更新时间： 2024-10-28 22:57:19

品牌	Logo	应用领域
艾迪悌 - IDT		/
页数	文件大小	规格书
22页	173K
描述
HIGH-SPEED 3.3V 8K x 8 DUAL-PORT STATIC RAM

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中文翻译

获取价格

数据手册

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IDT70V05L15J 数据手册

IDT70V05S/L

HIGH-SPEED 3.3V

8K x 8 DUAL-PORT

STATIC RAM

Features

◆

using the Master/Slave select when cascading more than

one device

M/S = VIH for BUSY output flag on Master

M/S = VIL for BUSY input on Slave

Interrupt Flag

On-chip port arbitration logic

Full on-chip hardware support of semaphore signaling

between ports

Fully asynchronous operation from either port

TTL-compatible, single 3.3V (±0.3V) power supply

Available in 68-pin PGA and PLCC, and a 64-pin TQFP

Industrial temperature range (-40°C to +85°C) is available

for selected speeds

True Dual-Ported memory cells which allow simultaneous

reads of the same memory location

High-speed access

◆

–

Commercial: 15/20/25/35/55ns (max.)

Industrial:20/25/35/55ns(max.)

◆

Low-power operation

–

IDT70V05S

Active:400mW(typ.)

Standby: 3.3mW (typ.)

IDT70V05L

◆

–

Active:380mW(typ.)

Standby: 660µW (typ.)

IDT70V05 easily expands data bus width to 16 bits or more

◆

Functional Block Diagram

OER

CER

OEL

CEL

R/W

I/O0L- I/O7L

I/O0R-I/O7R

I/O

Control

I/O

Control

(1,2)

BUSYL

BUSYR

A12L

A0L

A12R

A0R

Address

Decoder

MEMORY

ARRAY

Address

Decoder

ARBITRATION

INTERRUPT

SEMAPHORE

LOGIC

CEL

OEL

CER

OER

R/WR

R/WL

SEM

INTL

SEM

INTR

M/S

(2)

2941 drw 01

NOTES:

1. (MASTER): BUSY is output; (SLAVE): BUSY is input.

2. BUSY outputs and INT outputs are non-tri-stated push-pull.

MARCH 2000

DSC 2941/6

12 3 4 5 6 7...22

中文翻译

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