Datasheet > 存储 > SRAM> IDT70T3399S133DD

IDT70T3399S133DD

更新时间： 2024-10-28 22:57:19

品牌	Logo	应用领域
艾迪悌 - IDT		/
页数	文件大小	规格书
28页	476K
描述
HIGH-SPEED 2.5V 512/256/128K X 18 SYNCHRONOUS DUAL-PORT STATIC RAM WITH 3.3V OR 2.5V INTERFACE

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中文翻译

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数据手册

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IDT70T3399S133DD 数据手册

HIGH-SPEED 2.5V

512/256/128K X 18

SYNCHRONOUS

PRELIMINARY

IDT70T3339/19/99S

DUAL-PORT STATIC RAM

WITH 3.3V OR 2.5V INTERFACE

– Data input, address, byte enable and control registers

Features:

◆

– Self-timedwriteallowsfastcycletime

Separate byte controls for multiplexed bus and bus

matching compatibility

Dual Cycle Deselect (DCD) for Pipelined Output Mode

2.5V (±100mV) power supply for core

LVTTL compatible, selectable 3.3V (±150mV) or 2.5V

(±100mV) power supply for I/Os and control signals on

each port

Industrial temperature range (-40°C to +85°C) is

available at 166MHz and 133MHz

Available in a 256-pin Ball Grid Array (BGA), a 144-pin Thin

Quad Flatpack (TQFP) and 208-pin fine pitch Ball Grid Array

(fpBGA)

Supports JTAG features compliant with IEEE 1149.1

Due to limited pin count JTAG, Collision Detection and

Interrupt are not supported on the 144-pin TQFP package

True Dual-Port memory cells which allow simultaneous

◆

access of the same memory location

High-speed data access

◆

– Commercial: 3.4 (200MHz)/3.6ns (166MHz)/

4.2ns (133MHz)(max.)

– Industrial: 3.6ns (166MHz)/4.2ns (133MHz) (max.)

◆

Selectable Pipelined or Flow-Through output mode

◆

Counter enable and repeat features

◆

Dual chip enables allow for depth expansion without

additional logic

Interrupt and Collision Detection Flags

◆

Full synchronous operation on both ports

– 5ns cycle time, 200MHzoperation(14Gbps bandwidth)

– Fast 3.4ns clock to data out

– 1.5ns setup to clock and 0.5ns hold on all control, data, and

address inputs @ 200MHz

◆

FunctionalBlockDiagram

UBL

UBR

LBL

LBR

FT/PIPE

1b 0b

1a 0a

0a 1a

0b 1b

FT/PIPER

1/0

R/W

CE0L

CE0R

CE1R

CE1L

B B

W W

1/0

Dout0-8_L

Dout9-17_L

Dout0-8_R

Dout9-17_R

0a 1a

1b 0b 1a 0a

0/1

FT/PIPE

0/1

512/256/128K x 18

MEMORY

ARRAY

I/O0R - I/O17R

Din_L

I/O0L - I/O17L

Din_R

CLK

(1)

18R

(1)

18L

Counter/

Address

Reg.

Counter/

Address

Reg.

REPEAT

ADS

CNTEN

REPEAT

ADS

CNTEN

ADDR_R

ADDR_L

TDI

TCK

TMS

TRST

INTERRUPT

JTAG

COLLISION

DETECTION

LOGIC

CE1

TDO

CE1

R/W

COL

INT_L

COL_R

INT_R

5652 drw 01

(2)

ZZR

CONTROL

LOGIC

NOTES:

1. Address A18 is a NC for the IDT70T3319. Also, Addresses A18 and A17 are NC's for the IDT70T3399.

2. The sleep mode pin shuts off all dynamic inputs, except JTAG inputs, when asserted. All static inputs, i.e., PL/FTx and

NOVEMBER 2003

OPTx and the sleep mode pins themselves (ZZx) are not affected during sleep mode.

DSC-5652/3

12 3 4 5 6 7...28

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与IDT70T3399S133DD相关器件

型号	品牌	获取价格	描述	数据表
IDT70T3399S133DDI	IDT	获取价格	HIGH-SPEED 2.5V 512/256/128K X 18 SYNCHRONOUS DUAL-PORT STATIC RAM WITH 3.3V OR 2.5V INTER
IDT70T3399S166BC	IDT	获取价格	HIGH-SPEED 2.5V 512/256/128K X 18 SYNCHRONOUS DUAL-PORT STATIC RAM WITH 3.3V OR 2.5V INTER
IDT70T3399S166BC8	IDT	获取价格	Dual-Port SRAM, 128KX18, 12ns, CMOS, PBGA256, 17 X 17 MM, 1.40 MM HEIGHT, 1 MM PITCH, BGA-
IDT70T3399S166BCI	IDT	获取价格	HIGH-SPEED 2.5V 512/256/128K X 18 SYNCHRONOUS DUAL-PORT STATIC RAM WITH 3.3V OR 2.5V INTER
IDT70T3399S166BCI8	IDT	获取价格	Application Specific SRAM, 128KX18, 12ns, CMOS, PBGA256
IDT70T3399S166BF	IDT	获取价格	HIGH-SPEED 2.5V 512/256/128K X 18 SYNCHRONOUS DUAL-PORT STATIC RAM WITH 3.3V OR 2.5V INTER
IDT70T3399S166BFG	IDT	获取价格	Dual-Port SRAM, 128KX18, 3.6ns, CMOS, CBGA208, 15 X 15 MM X 1.4 MM, 0.80 MM PITCH, GREEN,
IDT70T3399S166BFG8	IDT	获取价格	Dual-Port SRAM, 128KX18, 12ns, CMOS, PBGA208, 15 X 15 MM, 1.40 MM HEIGHT, 0.80 MM PITCH, F
IDT70T3399S166BFGI	IDT	获取价格	Dual-Port SRAM, 128KX18, 12ns, PBGA208, 15 X 15 MM, 1.40 MM HEIGHT, 0.80 MM PITCH, FINE PI
IDT70T3399S166BFI	IDT	获取价格	HIGH-SPEED 2.5V 512/256/128K X 18 SYNCHRONOUS DUAL-PORT STATIC RAM WITH 3.3V OR 2.5V INTER

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