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IDT7052L20PFG PDF预览

IDT7052L20PFG

更新时间: 2024-11-28 14:51:23
品牌 Logo 应用领域
艾迪悌 - IDT 静态存储器内存集成电路
页数 文件大小 规格书
6页 72K
描述
Four-Port SRAM, 2KX8, 20ns, CMOS, PQFP120, 14 X 14 MM, 1.40 MM HEIGHT, GREEN, PLASTIC, TQFP-120

IDT7052L20PFG 技术参数

是否无铅: 不含铅是否Rohs认证: 符合
生命周期:Active零件包装代码:QFP
包装说明:LFQFP, QFP120,.63SQ,16针数:120
Reach Compliance Code:compliantECCN代码:EAR99
HTS代码:8542.32.00.41风险等级:5.21
最长访问时间:20 ns其他特性:AUTOMATIC POWER-DOWN
I/O 类型:COMMONJESD-30 代码:S-PQFP-G120
JESD-609代码:e3长度:14 mm
内存密度:16384 bit内存集成电路类型:FOUR-PORT SRAM
内存宽度:8湿度敏感等级:3
功能数量:1端口数量:4
端子数量:120字数:2048 words
字数代码:2000工作模式:ASYNCHRONOUS
最高工作温度:70 °C最低工作温度:
组织:2KX8输出特性:3-STATE
封装主体材料:PLASTIC/EPOXY封装代码:LFQFP
封装等效代码:QFP120,.63SQ,16封装形状:SQUARE
封装形式:FLATPACK, LOW PROFILE, FINE PITCH并行/串行:PARALLEL
峰值回流温度(摄氏度):260电源:5 V
认证状态:Not Qualified座面最大高度:1.6 mm
最大待机电流:0.0006 A最小待机电流:2 V
子类别:SRAMs最大压摆率:0.25 mA
最大供电电压 (Vsup):5.5 V最小供电电压 (Vsup):4.5 V
标称供电电压 (Vsup):5 V表面贴装:YES
技术:CMOS温度等级:COMMERCIAL
端子面层:Matte Tin (Sn) - annealed端子形式:GULL WING
端子节距:0.4 mm端子位置:QUAD
处于峰值回流温度下的最长时间:30宽度:14 mm
Base Number Matches:1

IDT7052L20PFG 数据手册

 浏览型号IDT7052L20PFG的Datasheet PDF文件第2页浏览型号IDT7052L20PFG的Datasheet PDF文件第3页浏览型号IDT7052L20PFG的Datasheet PDF文件第4页浏览型号IDT7052L20PFG的Datasheet PDF文件第5页浏览型号IDT7052L20PFG的Datasheet PDF文件第6页 
USING THE IDT7052/7054  
FOURPORT™ SRAMs  
APPLICATION  
NOTE  
IN DSP AND MATRIX  
AN-42  
PROCESSING APPLICATIONS  
By Tao Lin, Julie Lin, and Yupling Chung  
Introduction  
C
D
G
Most digital signal processing (DSP) algorithms have inherent par-  
allelism and may be pipelined. Usually, these algorithms are computa-  
tion intensive. In real-time applications, multiprocessor or parallel dis-  
tributed processor systems are commonly used to implement these  
DSP algorithms. In these types of systems it is necessary for different  
processors to randomly and independently access different locations at  
the same time in the same memory space. The IDT7052 (2Kx8) and  
IDT7054 (4Kx8) FourPort RAMs are powerful devices to efficiently  
and compactly implement the memory space in these applications. More-  
over, the IDT7052 and IDT7054 can increase the speed of these  
types of systems since the FourPort SRAMs are as fast as conven-  
tional SRAMs and eliminate the complex external logic which intro-  
duces extra delay in these systems. In this application note, we will  
demonstrate some examples of using the IDT7052 to implement a high  
performance FFT processor and a matrix multiplication engine.  
jΩ  
jΩ  
G = C + e  
H = C - e  
H
• D  
• D  
jΩ  
e
2684 drw 01  
Figure 1. The signal flow graph of the butterfly  
where C, D, G, and H are complex numbers. Figure 1 shows the  
signal flow graph of the butterfly with one complex multiplication and  
two complex additions. Given N = 2L input data samples x(0), x(1).....,  
x(N-1), the FFT algorithm performs the Discrete Fourier Transform on  
the input data to obtain the output data X(0), X(1)....., X(N-1) in L  
stages of computation. Each stage consists of N/2 butterfly operations.  
There are two basic versions of the FFT algorithm: decimation-in-time  
(DIT) and decimation-in-frequency (DIF). Each version of the algo-  
rithm can be implemented using two schemes: not-in-place computation  
and in-place computation. A detailed discussion of the FFT algorithm  
and its implementations is given in Reference (1).  
Using the IDT7052 in an FFT  
Processor  
The IDT7052 FourPort SRAM can dramatically simplify the design  
of a high-speed pipelined FFT processor. The basic operation of any  
FFT algorithm is the butterfly computation:  
Figure 2 shows the signal flow graph of the not-in-place computa-  
tion of the DIT FFT algorithm for N = 8(L=3). A close look at Figure 2  
will reveal the major strength of the not-in-place scheme. The signal  
G = C + ejW • D  
(1-1)  
H = C - ejW • D  
x(0)  
X(0)  
W0  
W0  
W0  
W0  
W2  
x(1)  
x(2)  
x(3)  
x(4)  
x(5)  
x(6)  
x(7)  
X(4)  
X(2)  
W0  
W0  
W1  
X(6)  
X(1)  
W2  
X(5)  
X(3)  
W0  
W2  
W3  
X(7)  
Stage 2  
Stage 3  
Stage 1  
Wk  
2684 drw 02  
-j2πk/N  
=
Figure 2. Signal Flow Graph of Not-In-Place Decimation-In-Time FFT for N=8  
MARCH 2000  
6.01  
1
2684/2  
©2000IntegratedDeviceTechnology,Inc.  

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