Datasheet > 存储 > SRAM> IDT7026S20JB

IDT7026S20JB

更新时间： 2024-11-20 23:01:07

品牌	Logo	应用领域
艾迪悌 - IDT		/
页数	文件大小	规格书
18页	239K
描述
HIGH-SPEED 16K x 16 DUAL-PORT STATIC RAM

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中文翻译

获取价格

数据手册

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IDT7026S20JB 数据手册

HIGH-SPEED

IDT7026S/L

16K x 16 DUAL-PORT

STATIC RAM

Integrated Device Technology, Inc.

FEATURES:

• True Dual-Ported memory cells which allow simulta-

neous access of the same memory location

• High-speed access

• IDT7026 easily expands data bus width to 32 bits or

more using the Master/Slave select when cascading

more than one device

— Military: 25/35/55ns (max.)

— Commercial: 20/25/35/55ns (max.)

• Low-power operation

• M/S = H for BUSY output flag on Master,

M/S = L for BUSY input on Slave

• On-chip port arbitration logic

— IDT7026S

• Full on-chip hardware support of semaphore signaling

between ports

Active: 750mW (typ.)

Standby: 5mW (typ.)

— IDT7026L

Active: 750mW (typ.)

Standby: 1mW (typ.)

• Separate upper-byte and lower-byte control for

multiplexed bus compatibility

• Fully asynchronous operation from either port

• TTL-compatible, single 5V (±10%) power supply

• Available in 84-pin PGA and 84-pin PLCC

• Industrial temperature range (–40°C to +85°C) is avail-

able, tested to military electrical specifications

FUNCTIONAL BLOCK DIAGRAM

OER

I/O8L-I/O15L

I/O0L-I/O7L

I/O8R-I/O15R

I/O0R-I/O7R

I/O

Control

I/O

Control

BUSY^(1,2)

BUSY ^(1,2)

13L

13R

Address

Decoder

MEMORY

ARRAY

Address

Decoder

ARBITRATION

SEMAPHORE

LOGIC

CEL

CER

SEM

M/S

2939 drw 01

NOTES:

1. (MASTER): BUSY is output; (SLAVE): BUSY is input.

2. BUSY outputs are non-tri-stated push-pull.

The IDT logo is a registered trademark of Integrated Device Technology, Inc.

MILITARY AND COMMERCIAL TEMPERATURE RANGES

OCTOBER 1996

For latest information contact IDT’s web site at www.idt.com or fax-on-demand at 408-492-8391.

DSC 2939/3

6.17

12 3 4 5 6 7...18

中文翻译

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