Datasheet > IDT7026S25JI

IDT7026S25JI

更新时间： 2024-11-25 19:50:35

品牌	Logo	应用领域
艾迪悌 - IDT		静态存储器
页数	文件大小	规格书
18页	267K
描述
Dual-Port SRAM, 16KX16, 25ns, CMOS, PQCC84, PLASTIC, LCC-84

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中文翻译

获取价格

技术参数
数据手册

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IDT7026S25JI 技术参数

是否无铅：	含铅	是否Rohs认证：	不符合
生命周期：	Obsolete	零件包装代码：	LCC
包装说明：	QCCJ, LDCC84,1.2SQ	针数：	84
Reach Compliance Code：	not_compliant	ECCN代码：	EAR99
HTS代码：	8542.32.00.41	风险等级：	5.26
Base Number Matches：	1

IDT7026S25JI 数据手册

HIGH-SPEED

IDT7026S/L

16K X 16 DUAL-PORT

STATIC RAM

Features

◆

True Dual-Ported memory cells which allow simultaneous

access of the same memory location

High-speed access

IDT7026 easily expands data bus width to 32 bits or more

using the Master/Slave select when cascading more than

one device

M/S = H for BUSY output flag on Master,

M/S = L for BUSY input on Slave

On-chip port arbitration logic

Full on-chip hardware support of semaphore signaling

between ports

Fully asynchronous operation from either port

TTL-compatible, single 5V (±10%) power supply

Available in 84-pin PGA and 84-pin PLCC

Industrial temperature range (-40°C to +85°C) is available

for selected speeds

◆

– Commercial: 15/20/25/35/55ns (max.)

– Industrial: 20/25/35/55ns (max.)

– Military: 20/25/35/55ns (max.)

Low-power operation

◆

– IDT7026S

◆

Active: 750mW (typ.)

Standby: 5mW (typ.)

– IDT7026L

Active: 750mW (typ.)

Standby: 1mW (typ.)

Separate upper-byte and lower-byte control for multi-

plexed bus compatibility

◆

FunctionalBlockDiagram

UBL

CER

I/O8L-I/O15L

I/O0L-I/O7L

I/O8R-I/O15R

I/O

Control

I/O

Control

I/O0R-I/O7R

(1,2)

BUSY

13R

13L

Address

Decoder

MEMORY

ARRAY

Address

Decoder

A0R

ARBITRATION

SEMAPHORE

LOGIC

SEMR

SEM

M/S

2939 drw 01

NOTES:

1. (MASTER): BUSY is output; (SLAVE): BUSY is input.

2. BUSY outputs are non-tri-stated push-pull.

DECEMBER 2002

DSC 2939/12

12 3 4 5 6 7...18

中文翻译

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