IDT59910A-5SOC

更新时间： 2024-11-09 13:08:39

品牌	Logo	应用领域
艾迪悌 - IDT		时钟驱动器
页数	文件大小	规格书
6页	54K
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中文翻译

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数据手册

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IDT59910A-5SOC 数据手册

IDT59910A

COMMERCIALANDINDUSTRIALTEMPERATURERANGES

LOWSKEWPLLCLOCKDRIVERTURBOCLOCKJR.

LOW SKEW

IDT59910A

PLL CLOCK DRIVER

TURBOCLOCK™ JR.

FEATURES:

DESCRIPTION:

• Eight zero delay outputs

The IDT59910A is a high fanout phase lock loop clock driver in-

tended for high performance computing and data-communications appli-

cations. The IDT59910A has eight zero delay TTL outputs.

• Selectable positive or negative edge synchronization

• Synchronous output enable

• Output frequency: 15MHz to 100MHz

• TTL outputs

• 3 skew grades:

IDT59910A-2: tSKEW0<250ps

The IDT59910A maintains Cypress CY7B9910 compatibility while pro-

viding two additional features: Synchronous Output Enable (GND/sOE),

and Positive/Negative Edge Synchronization (VCCQ/PE). When the GND/

sOE pin is held low, all the outputs are synchronously enabled (CY7B9910

compatibility). However, if GND/sOE is held high, all the outputs except

Q2 and Q3 are synchronously disabled.

Furthermore, when the VCCQ/PE is held high, all the outputs are syn-

chronized with the positive edge of the REF clock input (CY7B9910

compatibility). When V^CCQ/PE is held low, all the outputs are synchro-

nized with the negative edge of REF.

The FB signal is compared with the input REF signal at the phase

detector in order to drive the VCO. Phase differences cause the VCO of

the PLL to adjust upwards or downwards accordingly.

An internal loop filter moderates the response of the VCO to the

phase detector. The loop filter transfer function has been chosen to

provide minimal jitter (or frequency variation) while still providing accu-

rate responses to input frequency changes.

IDT59910A-5: tSKEW0<500ps

IDT59910A-7: tSKEW0<750ps

• 3-level inputs for PLL range control

• PLL bypass for DC testing

• External feedback, internal loop filter

• 46mA IOL high drive outputs

• Low Jitter: <200ps peak-to-peak

• Outputs drive 50Ω terminated lines

• Pin-compatible with Cypress CY7B9910

• Available in SOIC package

FUNCTIONALBLOCKDIAGRAM

VCCQ/PE

GND/sOE

PLL

REF

TheIDTlogoisaregisteredtrademarkofIntegratedDeviceTechnology,Inc.

COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES

SEPTEMBER 2001

2001 Integrated Device Technology, Inc.

DSC 5845/1

12 3 4 5 6

中文翻译

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与IDT59910A-5SOC相关器件

型号	品牌	获取价格	描述	数据表
IDT59910A-5SOI	IDT	获取价格	LOW SKEW PLL CLOCK DRIVER TURBOCLOCK JR.
IDT59910A-7SO	IDT	获取价格	LOW SKEW PLL CLOCK DRIVER TURBOCLOCK JR.
IDT59910A-7SOI	IDT	获取价格	LOW SKEW PLL CLOCK DRIVER TURBOCLOCK JR.
IDT5991A	IDT	获取价格	PROGRAMMABLE SKEW PLL CLOCK DRIVER TURBOCLOCK
IDT5991A-2J	IDT	获取价格	PLL Based Clock Driver, 5991 Series, 8 True Output(s), 0 Inverted Output(s), PQCC32, PLAST
IDT5991A-2J8	IDT	获取价格	PLL Based Clock Driver, 5991 Series, 8 True Output(s), 0 Inverted Output(s), PQCC32, PLAST
IDT5991A-2JG	IDT	获取价格	PLL Based Clock Driver, 5991 Series, 8 True Output(s), 0 Inverted Output(s), PQCC32, GREEN
IDT5991A-2JG8	IDT	获取价格	PLL Based Clock Driver, 5991 Series, 8 True Output(s), 0 Inverted Output(s), PQCC32, PLAST
IDT5991A-2JI	IDT	获取价格	PROGRAMMABLE SKEW PLL CLOCK DRIVER TURBOCLOCK
IDT5991A-2JRC	IDT	获取价格	PLL Based Clock Driver, 8 True Output(s), 0 Inverted Output(s), PQCC32, PLASTIC, LCC-32

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