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IDT5991A-7JRI PDF预览

IDT5991A-7JRI

更新时间: 2024-11-07 13:08:39
品牌 Logo 应用领域
艾迪悌 - IDT 时钟驱动器逻辑集成电路
页数 文件大小 规格书
8页 68K
描述
PLL Based Clock Driver, 8 True Output(s), 0 Inverted Output(s), PQCC32, PLASTIC, LCC-32

IDT5991A-7JRI 技术参数

是否无铅:含铅是否Rohs认证:不符合
生命周期:Obsolete零件包装代码:QFJ
包装说明:PLASTIC, LCC-32针数:32
Reach Compliance Code:compliantHTS代码:8542.39.00.01
风险等级:5.72Is Samacsys:N
输入调节:STANDARDJESD-30 代码:R-PQCC-J32
JESD-609代码:e0长度:13.97 mm
逻辑集成电路类型:PLL BASED CLOCK DRIVER功能数量:1
反相输出次数:端子数量:32
实输出次数:8最高工作温度:85 °C
最低工作温度:-40 °C封装主体材料:PLASTIC/EPOXY
封装代码:QCCJ封装形状:RECTANGULAR
封装形式:CHIP CARRIER峰值回流温度(摄氏度):225
认证状态:Not QualifiedSame Edge Skew-Max(tskwd):0.75 ns
座面最大高度:3.55 mm最大供电电压 (Vsup):5.5 V
最小供电电压 (Vsup):4.5 V标称供电电压 (Vsup):5 V
表面贴装:YES温度等级:INDUSTRIAL
端子面层:TIN LEAD端子形式:J BEND
端子节距:1.27 mm端子位置:QUAD
处于峰值回流温度下的最长时间:30宽度:11.43 mm
最小 fmax:100 MHzBase Number Matches:1

IDT5991A-7JRI 数据手册

 浏览型号IDT5991A-7JRI的Datasheet PDF文件第2页浏览型号IDT5991A-7JRI的Datasheet PDF文件第3页浏览型号IDT5991A-7JRI的Datasheet PDF文件第4页浏览型号IDT5991A-7JRI的Datasheet PDF文件第5页浏览型号IDT5991A-7JRI的Datasheet PDF文件第6页浏览型号IDT5991A-7JRI的Datasheet PDF文件第7页 
IDT5991A  
PROGRAMMABLE SKEW  
PLL CLOCK DRIVER  
TURBOCLOCK™  
FEATURES:  
DESCRIPTION:  
• 4 pairs of programmable skew outputs  
• Low skew: 200ps same pair, 250ps all outputs  
• Selectable positive or negative edge synchronization:  
Excellent for DSP applications  
The IDT5991A is a high fanout PLL based clock driver intended for  
high performance computing and data-communications applications. A  
key feature of the programmable skew is the ability of outputs to lead or  
lag the REF input signal. The IDT5991A has eight programmable skew  
outputs in four banks of 2. Skew is controlled by 3-level input signals  
that may be hard-wired to appropriate HIGH-MID-LOW levels.  
The IDT5991A maintains Cypress CY7B991 compatibility while pro-  
viding two additional features: Synchronous Output Enable (GND/sOE),  
and Positive/Negative Edge Synchronization (VCCQ/PE). When the GND/  
sOE pin is held low, all the outputs are synchronously enabled (CY7B991  
compatibility). However, if GND/sOE is held high, all the outputs except  
3Q0 and 3Q1 are synchronously disabled.  
• Synchronous output enable  
• Output frequency: 3.75MHz to 100MHz  
• 2x, 4x, 1/2, and 1/4 outputs  
• 5V with TTL outputs  
• 3 skew grades:  
IDT5991A-2: tSKEW0<250ps  
IDT5991A-5: tSKEW0<500ps  
IDT5991A-7: tSKEW0<750ps  
• 3-level inputs for skew and PLL range control  
• PLL bypass for DC testing  
Furthermore, when the VCCQ/PE is held high, all the outputs are syn-  
chronized with the positive edge of the REF clock input (CY7B991 com-  
patibility). When VCCQ/PE is held low, all the outputs are synchronized  
with the negative edge of REF.  
• External feedback, internal loop filter  
• 46mA IOL high drive outputs  
• Low Jitter: <200ps peak-to-peak  
• Outputs drive 50terminated lines  
• Pin-compatible with Cypress CY7B991  
• Available in PLCC Package  
FUNCTIONALBLOCKDIAGRAM  
GND/sOE  
1Q0  
Skew  
Select  
1Q1  
3
3
3
1F1:0  
2F1:0  
3F1:0  
4F1:0  
VCCQ/PE  
2Q0  
2Q1  
Skew  
Select  
3
REF  
PLL  
FB  
3Q0  
3Q1  
Skew  
Select  
3
3
3
3
FS  
4Q0  
4Q1  
Skew  
Select  
3
TheIDTlogoisaregisteredtrademarkofIntegratedDeviceTechnology,Inc.  
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES  
AUGUST 2001  
1
c
2001 Integrated Device Technology, Inc.  
DSC 5843/1  

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