IDT5992A-2J

更新时间： 2024-02-11 09:08:41

品牌	Logo	应用领域
艾迪悌 - IDT		时钟驱动器逻辑集成电路
页数	文件大小	规格书
8页	70K
描述
PROGRAMMABLE SKEW PLL CLOCK DRIVER TURBOCLOCK-TM

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IDT5992A-2J 技术参数

是否Rohs认证：	不符合	生命周期：	Obsolete
Reach Compliance Code：	not_compliant	风险等级：	5.92
JESD-609代码：	e0	湿度敏感等级：	1
端子面层：	Tin/Lead (Sn85Pb15)	Base Number Matches：	1

IDT5992A-2J 数据手册

IDT5992A

COMMERCIALANDINDUSTRIALTEMPERATURERANGES

PROGRAMMABLESKEWPLLCLOCKDRIVERTURBOCLOCK

IDT5992A

PROGRAMMABLE SKEW

PLL CLOCK DRIVER

TURBOCLOCK™

FEATURES:

DESCRIPTION:

• 4 pairs of programmable skew outputs

• Low skew: 200ps same pair, 250ps all outputs

• Selectable positive or negative edge synchronization:

Excellent for DSP applications

The IDT5992A is a high fanout PLL based clock driver intended for

high performance computing and data-communications applications. A

key feature of the programmable skew is the ability of outputs to lead or

lag the REF input signal. The IDT5992A has eight programmable skew

outputs in four banks of 2. Skew is controlled by 3-level input signals

that may be hard-wired to appropriate HIGH-MID-LOW levels.

The IDT5992A maintains Cypress CY7B992 compatibility while pro-

viding two additional features: Synchronous Output Enable (GND/sOE),

and Positive/Negative Edge Synchronization (VDDQ/PE). When the GND/

sOE pin is held low, all the outputs are synchronously enabled (CY7B992

compatibility). However, if GND/sOE is held high, all the outputs except

3Q0 and 3Q1 are synchronously disabled.

• Synchronous output enable

• Output frequency: 3.75MHz to 100MHz

• 2x, 4x, 1/2, and 1/4 outputs

• 5V with CMOS outputs

• 3 skew grades:

IDT5992A-2: tSKEW0<250ps

IDT5992A-5: tSKEW0<500ps

IDT5992A-7: tSKEW0<750ps

• 3-level inputs for skew and PLL range control

• PLL bypass for DC testing

Furthermore, when the V^DDQ/PE is held high, all the outputs are syn-

chronized with the positive edge of the REF clock input (CY7B992 com-

patibility). When VDDQ/PE is held low, all the outputs are synchronized

with the negative edge of REF.

• External feedback, internal loop filter

• 46mA IOL high drive outputs

• Low Jitter: <200ps peak-to-peak

• Outputs drive 50Ω terminated lines

• Pin-compatible with Cypress CY7B992

• Available in PLCC Package

FUNCTIONALBLOCKDIAGRAM

GND/sOE

1Q0

Skew

Select

1Q1

1F1:0

VDDQ /PE

2Q0

2Q1

Skew

Select

REF

PLL

2F1:0

3Q0

3Q1

Skew

Select

3F1:0

4Q0

4Q1

Skew

Select

4F1:0

TheIDTlogoisaregisteredtrademarkofIntegratedDeviceTechnology,Inc.

COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES

AUGUST 2001

2001 Integrated Device Technology, Inc.

DSC 5391/1

12 3 4 5 6 7 8

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与IDT5992A-2J相关器件

型号	品牌	描述	获取价格	数据表
IDT5992A-2J8	IDT	PLL Based Clock Driver, 8 True Output(s), 0 Inverted Output(s), PQCC32, PLASTIC, LCC-32	获取价格
IDT5992A-2JI	IDT	PROGRAMMABLE SKEW PLL CLOCK DRIVER TURBOCLOCK-TM	获取价格
IDT5992A-2JRC	IDT	暂无描述	获取价格
IDT5992A-5J	IDT	PROGRAMMABLE SKEW PLL CLOCK DRIVER TURBOCLOCK-TM	获取价格
IDT5992A-5JI	IDT	PLL Based Clock Driver, 8 True Output(s), 0 Inverted Output(s), PQCC32, PLASTIC, LCC-32	获取价格
IDT5992A-5JI8	IDT	PLL Based Clock Driver, 8 True Output(s), 0 Inverted Output(s), PQCC32, PLASTIC, LCC-32	获取价格

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