IDT5992A
PROGRAMMABLESKEWPLLCLOCKDRIVERTURBOCLOCK
COMMERCIALANDINDUSTRIALTEMPERATURERANGES
PINCONFIGURATION
ABSOLUTEMAXIMUMRATINGS(1)
Symbol
Description
Supply Voltage to Ground
DC Input Voltage
Max
–0.5 to +7
–0.5 to +7
0.8
Unit
V
VI
V
4
3
2
1
32 31 30
Maximum Power Dissipation (TA = 85°C)
Storage Temperature
W
3F1
4F0
5
29
28
27
26
25
24
23
22
21
2F0
TSTG
–65 to +150
°C
6
GND/sOE
1F1
NOTE:
4F1
7
1. Stresses beyond those listed under ABSOLUTE MAXIMUM RATINGS may cause
permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions above those indicated in the
operational sections of this specification is not implied. Exposure to absolute-
maximum-rated conditions for extended periods may affect device reliability.
VDDQ/PE
8
1F0
VDDN
VDDN
4Q1
9
10
11
12
13
1Q0
4Q0
1Q1
GND
GND
GND
GND
14 15 16 17 18 19 20
CAPACITANCE(TA = +25°C, f = 1MHz, VIN = 0V)
Parameter Description
Typ.
Max.
Unit
CIN
InputCapacitance
5
7
pF
NOTE:
PLCC
TOP VIEW
1. Capacitance applies to all inputs except TEST, FS, and nF1:0.
PINDESCRIPTION
Pin Name
REF
Type
IN
Description
ReferenceClockInput
FeedbackInput
FB
IN
TEST(1)
IN
When MID or HIGH, disables PLL (except for conditions of Note 1). REF goes to all outputs. Skew selections (see Control
SummaryTable)remainineffect. SetLOWfornormaloperation.
GND/ sOE (1)
IN
IN
Synchronous Output Enable. When HIGH, it stops clock outputs (except 3Q0 and 3Q1) in a LOW state - 3Q0 and 3Q1 may be used as
thefeedbacksignaltomaintainphaselock. WhenTESTisheldatMIDlevelandGND/sOEisHIGH,thenF[1:0]pinsactasoutputdisable
controls for individual banks when nF[1:0] = LL. Set GND/sOE LOW for normal operation.
Selectablepositiveornegativeedgecontrol. WhenLOW/HIGHtheoutputsaresynchronizedwiththenegative/positiveedgeofthe
referenceclock.
VDDQ/PE
nF[1:0]
FS
IN
3-levelinputsforselecting1of9skewtapsorfrequencyfunctions
IN
Selectsappropriateoscillatorcircuitbasedonanticipatedfrequencyrange. (SeePLLProgrammableSkewRange.)
Fourbanksoftwooutputswithprogrammableskew
nQ[1:0]
VDDN
VDDQ
GND
OUT
PWR
PWR
PWR
Powersupplyforoutputbuffers
Powersupplyforphaselockedloopandotherinternalcircuitry
Ground
NOTE:
1.When TEST = MID and GND/sOE = HIGH, PLL remains active with nF[1:0] = LL functioning as an output disable control for individual output banks. Skew selections remain
in effect unless nF[1:0] = LL.
PROGRAMMABLESKEW
Output skew with respect to the REF input is adjustable to compensate to minimize the number of control pins, 3-level inputs (HIGH-MID-LOW)
for PCB trace delays, backplane propagation delays or to accommodate are used, they are intended for but not restricted to hard-wiring. Undriven
requirements for special timing relationships between clocked compo- 3-level inputs default to the MID level. Where programmable skew is
nents. Skew is selectable as a multiple of a time unit tU which is of the not a requirement, the control pins can be left open for the zero skew
order of a nanosecond (see PLL Programmable Skew Range and Resolution default setting. The Control Summary Table shows how to select specific
Table). There are nine skew configurations available for each output skew taps by using the nF1:0 control pins.
pair. These configurations are chosen by the nF1:0 control pins. In order
2
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