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ICS9250F-28-T PDF预览

ICS9250F-28-T

更新时间： 2024-11-08 23:57:47
品牌 Logo 应用领域
其他 - ETC /
页数 文件大小 规格书
17页 198K
描述
Peripheral IC

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ICS9250F-28-T 数据手册

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Integrated  
Circuit  
Systems, Inc.  
ICS9250-28  
Frequency Generator & Integrated Buffers for Celeron & PII/III™  
Recommended Application:  
Pin Configuration  
810/810E and 815 type chipset.  
IOAPIC  
VDDL  
GND  
1
2
56  
55  
54  
53  
52  
51  
50  
49  
48  
47  
46  
45  
44  
43  
42  
41  
40  
39  
38  
37  
36  
35  
34  
33  
32  
31  
30  
29  
VDDL  
GND  
Output Features:  
2 CPU (2.5V) (up to 133MHz achievable through I2C)  
3
4
5
6
7
8
9
CPUCLK0  
CPUCLK1  
GND  
SDRAM0  
SDRAM1  
VDDSDR  
GND  
SDRAM2  
SDRAM3  
SDRAM4  
VDDSDR  
GND  
SDRAM5  
SDRAM6  
VDDSDR  
GND  
SDRAM7  
SDRAM8  
SDRAM9  
VDDSDR  
GND  
SDRAM10  
SDRAM11  
VDDSDR  
GND  
•
•
*FS1/REF0  
VDDREF  
X1  
13 SDRAM (3.3V) (up to 133MHz achievable  
through I2C)  
X2  
GND  
•
•
•
•
•
2 PCI (3.3 V) @33.3MHz  
VDD3V66  
3V66_0  
3V66_1  
3V66_2  
GND  
VDDPCI  
PCICLK0  
PCICLK1  
GND  
1 IOAPIC (2.5V) @ 33.3 MHz  
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
21  
22  
23  
24  
25  
26  
27  
28  
3 Hublink clocks (3.3 V) @ 66.6 MHz  
2 (3.3V) @ 48 MHz (Non spread spectrum)  
1 REF (3.3V) @ 14.318 MHz  
Features:  
•
Supports spread spectrum modulation,  
0 to -0.5% down spread.  
FS0  
GND  
VDDA  
PD#  
•
•
•
•
I2C support for power management  
Efficient power management scheme through PD#  
Uses external 14.138 MHz crystal  
Alternate frequency selections available through I2C  
control.  
SCLK  
SDATA  
GND  
VDD48  
48MHz_0  
48MHz_1  
FS2  
SDRAM12  
56-Pin 300mil SSOP  
* This input has a 50KW pull-down to GND.  
Functionality  
Block Diagram  
FS2  
FS0  
FS1  
Function  
0
0
0
1
X
X
Tristate  
Test  
X1  
X2  
XTAL  
OSC  
REF0  
Active CPU = 66MHz  
SDRAM = 100MHz  
1
1
1
1
0
1
0
1
0
0
1
1
PLL1  
Spread  
Spectrum  
Active CPU = 100MHz  
SDRAM = 100MHz  
/2  
/3  
Active CPU = 133MHz  
SDRAM = 133MHz  
CPU66/100/133 [1:0]  
2
3V66 (2:0)  
FS(2:0)  
PD#  
3
Control  
Logic  
Active CPU = 133MHz  
SDRAM = 100MHz  
SDRAM (12:0)  
13  
Config  
Reg  
PCICLK (1:0)  
IOAPIC  
/2  
2
SDATA  
SCLK  
Power Groups  
/2  
Analog  
Digital  
VDD3V66, VDDPCI  
VDDSDR, VDDL  
VDDREF = X1, X2  
VDDA = PLL1  
VDD48 = PLL2  
48MHz (1:0)  
PLL2  
2
ICS reserves the right to make changes in the device data identified in  
this publication without further notice. ICS advises its customers to  
obtain the latest version of all device data to verify that any  
9250-28 Rev B 10/26/00  
Third party brands and names are the property of their respective owners.  
information being relied upon by the customer is current and accurate.  
1234567...17

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