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ICS9250YF-11 PDF预览

ICS9250YF-11

更新时间： 2024-02-15 14:44:35
品牌 Logo 应用领域
艾迪悌 - IDT 时钟光电二极管外围集成电路晶体
页数 文件大小 规格书
8页 194K
描述
Processor Specific Clock Generator, 133.3MHz, PDSO56, 0.300 INCH, SSOP-56

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ICS9250YF-11 技术参数

是否无铅： 含铅是否Rohs认证： 不符合
生命周期：Obsolete零件包装代码：SSOP
包装说明：SSOP,针数：56
Reach Compliance Code：compliantECCN代码：EAR99
HTS代码：8542.39.00.01风险等级：5.79
JESD-30 代码：R-PDSO-G56JESD-609代码：e0
长度：18.415 mm端子数量：56
最高工作温度：70 °C最低工作温度：
最大输出时钟频率：133.3 MHz封装主体材料：PLASTIC/EPOXY
封装代码：SSOP封装形状：RECTANGULAR
封装形式：SMALL OUTLINE, SHRINK PITCH峰值回流温度（摄氏度）：225
主时钟/晶体标称频率：14.318 MHz认证状态：Not Qualified
座面最大高度：2.794 mm最大供电电压：2.625 V
最小供电电压：2.375 V标称供电电压：2.5 V
表面贴装：YES技术：CMOS
温度等级：COMMERCIAL端子面层：Tin/Lead (Sn/Pb)
端子形式：GULL WING端子节距：0.635 mm
端子位置：DUAL处于峰值回流温度下的最长时间：30
宽度：7.5 mmuPs/uCs/外围集成电路类型：CLOCK GENERATOR, PROCESSOR SPECIFIC
Base Number Matches：1

ICS9250YF-11 数据手册

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Integrated  
Circuit  
Systems, Inc.  
ICS9250-11  
Frequency Timing Generator for PENTIUM II/III™ Systems  
General Description  
Features  
The ICS9250-11 is a main clock synthesizer chip for Pentium  
II based systems using Rambus Interface DRAMs. This chip  
provides all the clocks required for such a system when used  
with a Direct Rambus Clock Generator (DRCG) chip such as  
the ICS9212-01, 02, 03 and a PCI buffer 9112-17.  
•
Generates the following system clocks:  
- 6 - CPU Clocks 100/133MHz (2.5V).  
- 2 - CPU/2 output for synchronous memory  
reference (2.5V).  
- 4 - fixed frequency Clocks @ 66.6MHz (3.3V).  
- 2 - fixed frequency Clocks @ 33.3MHz (3.3V).  
- 6 - IOAPIC Clocks @ ¼ of CPUCLK or 16.667MHz,  
synchronous to CPU Clock (2.5V)  
- 1 - 48MHz Clock (3.3V)  
Spread Spectrum may be enabled by driving the SPREAD#  
pin active. Spread spectrum typically reduces system EMI by  
8dB to 10dB. This simplifies EMI qualification without  
resorting to board design iterations or costly shielding. The  
ICS9250-11 employs a proprietary closed loop design, which  
tightly controls the percentage of spreading over process and  
temperature variations.  
- 2 - REF Clocks @ 14.31818MHz  
•
•
0.5% typical down spread modulation on CPU, PCI,  
IOAPIC, 3V66 and CPU/2 output clocks.  
The CPU/2 clocks are inputs to the DRCG.  
Uses external 14.318MHz crystal.  
Block Diagram  
X1  
REF (0:1)  
OSC  
2
X2  
Pin Configuration  
CPUCLK (0:5)  
IOAPIC(0:5)  
6
PLL  
Spread  
Spectrum  
SPREAD#  
/ 2  
/ 3  
/ 4  
/ 2  
C
o
n
t
6
2
SEL 133/100#  
SEL(0:1)  
r
o
l
CPU/2 (0:1)  
3V66 (0:3)  
/ 2  
/ 3  
/ 2  
4
2
/ 2  
3V33 (0:1)  
48MHz  
PLL2  
Power Groups:  
VDDREF, GNDREF = REF, X1, X2  
VDD66, GND66 = 3V66  
VDD33, GND33 = 3V33  
VDD48, GND48 = 48MHz  
56-pin SSOP  
VDDCOR, GNDCOR = PLL Core  
VDDLCPU, GNDLCPU = CPUCLK  
VDDLCPU/2 , GNDLCPU/2 = CPU/2  
VDDLAPIC, GNDAPIC = IOAPIC  
ICS reserves the right to make changes in the device data identified in this  
publication without further notice. ICS advises its customers to obtain the  
latest version of all device data to verify that any information being relied  
upon by the customer is current and accurate.  
9250-11 Rev C 3/20/00  
Third party brands and names are the property of their respective owners.  
12345678

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