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ICS9250YF-13LF PDF预览

ICS9250YF-13LF

更新时间: 2024-11-09 15:45:27
品牌 Logo 应用领域
艾迪悌 - IDT 时钟光电二极管外围集成电路晶体
页数 文件大小 规格书
15页 563K
描述
Processor Specific Clock Generator, 90MHz, PDSO56, 0.300 INCH, SSOP-56

ICS9250YF-13LF 技术参数

是否无铅: 不含铅是否Rohs认证: 符合
生命周期:Obsolete零件包装代码:SSOP
包装说明:SSOP,针数:56
Reach Compliance Code:compliantECCN代码:EAR99
HTS代码:8542.39.00.01风险等级:5.73
其他特性:CAN ALSO OPERATE AT 3.3V SUPPLYJESD-30 代码:R-PDSO-G56
JESD-609代码:e3长度:18.415 mm
端子数量:56最高工作温度:70 °C
最低工作温度:最大输出时钟频率:90 MHz
封装主体材料:PLASTIC/EPOXY封装代码:SSOP
封装形状:RECTANGULAR封装形式:SMALL OUTLINE, SHRINK PITCH
峰值回流温度(摄氏度):260主时钟/晶体标称频率:16 MHz
认证状态:Not Qualified座面最大高度:2.794 mm
最大供电电压:2.625 V最小供电电压:2.375 V
标称供电电压:2.5 V表面贴装:YES
技术:CMOS温度等级:COMMERCIAL
端子面层:Matte Tin (Sn)端子形式:GULL WING
端子节距:0.635 mm端子位置:DUAL
处于峰值回流温度下的最长时间:30宽度:7.5 mm
uPs/uCs/外围集成电路类型:CLOCK GENERATOR, PROCESSOR SPECIFICBase Number Matches:1

ICS9250YF-13LF 数据手册

 浏览型号ICS9250YF-13LF的Datasheet PDF文件第2页浏览型号ICS9250YF-13LF的Datasheet PDF文件第3页浏览型号ICS9250YF-13LF的Datasheet PDF文件第4页浏览型号ICS9250YF-13LF的Datasheet PDF文件第5页浏览型号ICS9250YF-13LF的Datasheet PDF文件第6页浏览型号ICS9250YF-13LF的Datasheet PDF文件第7页 
Integrated  
Circuit  
Systems, Inc.  
ICS9250-13  
Frequency Generator & Integrated Buffers for PENTIUM/ProTM  
General Description  
Features  
•
3.3Voutputs:SDRAM, PCI, REF, 48/24MHz  
2.5Vor3.3Voutputs:CPU  
The ICS9250-13 generates all clocks required for high speed  
RISCorCISCmicroprocessorsystemssuchasIntel PentiumPro  
orCyrix. Eightdifferentreferencefrequencymultiplyingfactors  
are externally selectable with smooth frequency transitions.  
•
•
•
•
20 ohm CPU clock output impedance  
20 ohm PCI clock output impedance  
Skew from CPU (earlier) to PCI clock - 1 to 4 ns,  
center 2.6 ns.  
Spread spectrum may be enabled through I2C programming.  
Spread spectrum typically reduces system EMI by 8dB to  
10dB. This simplifies EMI qualification without resorting to  
board design iterations or costly shielding. The ICS9250-13  
employs a proprietary closed loop design, which tightly  
controls the percentage of spreading over process and  
temperature variations.  
•
•
•
•
No external load cap for CL=18pF crystals  
±250 ps CPU, PCI clock skew  
400ps (cycle to cycle) CPU jitter  
Smooth frequency switch, with selections from  
50to83.3MHzCPU.  
•
•
•
•
•
I2C interface for programming  
2ms power up clock stable time  
Clock duty cycle 45-55%.  
56pin300milSSOPpackage  
3.3V operation, 5V tolerant input.  
Block Diagram  
Recomended Application:  
•
440LX/EX type chipset Motherboard single chip  
clock solution.  
Pin Configuration  
Power Groups  
56-Pin SSOP  
VDDREF=REF(0:1),X1,X2  
VDDPCI=PCICLK_F,PCICLK(0:5)  
VDDSDR=SDRAM(0:11), supplyforPLLcore,  
VDD48=24MHz,48MHz  
* Internal Pull-up Resistor of  
120K to VDD on indicated inputs  
VDDLIOAPIC=IOAPIC  
VDDL2CPU= CPUCLK(0:3)  
Pentium is a trademark of Intel Corporation  
I2C is a trademark of Philips Corporation  
ICS reserves the right to make changes in the device data identified in  
this publication without further notice. ICS advises its customers to  
obtain the latest version of all device data to verify that any  
9250-13RevA3/25/99  
information being relied upon by the customer is current and accurate.  

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