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ICS9250YF-09LF PDF预览

ICS9250YF-09LF

更新时间: 2024-02-19 22:39:52
品牌 Logo 应用领域
艾迪悌 - IDT 时钟光电二极管外围集成电路晶体
页数 文件大小 规格书
12页 336K
描述
Processor Specific Clock Generator, 133.32MHz, PDSO56, 0.300 INCH, SSOP-56

ICS9250YF-09LF 技术参数

是否无铅:不含铅是否Rohs认证:符合
生命周期:Obsolete零件包装代码:SSOP
包装说明:SSOP,针数:56
Reach Compliance Code:compliantECCN代码:EAR99
HTS代码:8542.39.00.01风险等级:5.73
Is Samacsys:NJESD-30 代码:R-PDSO-G56
JESD-609代码:e3长度:18.415 mm
端子数量:56最高工作温度:70 °C
最低工作温度:最大输出时钟频率:133.32 MHz
封装主体材料:PLASTIC/EPOXY封装代码:SSOP
封装形状:RECTANGULAR封装形式:SMALL OUTLINE, SHRINK PITCH
峰值回流温度(摄氏度):260主时钟/晶体标称频率:16 MHz
认证状态:Not Qualified座面最大高度:2.794 mm
最大供电电压:3.45 V最小供电电压:3.15 V
标称供电电压:3.3 V表面贴装:YES
技术:CMOS温度等级:COMMERCIAL
端子面层:Matte Tin (Sn)端子形式:GULL WING
端子节距:0.635 mm端子位置:DUAL
处于峰值回流温度下的最长时间:30宽度:7.5 mm
uPs/uCs/外围集成电路类型:CLOCK GENERATOR, PROCESSOR SPECIFICBase Number Matches:1

ICS9250YF-09LF 数据手册

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Integrated  
Circuit  
Systems, Inc.  
ICS9250-09  
Frequency Timing Generator for PENTIUM II Systems  
General Description  
Features  
•
Generates the following system clocks:  
The ICS9250-09 is a main clock synthesizer chip for  
Pentium II based systems using Rambus Interface DRAMs.  
This chip provides all the clocks required for such a system  
when used with a Direct Rambus Clock Generator(DRCG)  
chip such as the ICS9211-01.  
- 4CPUclocks(2.5V,100/133MHz)  
- 8 PCI clocks, including 1 free-running (3.3V, 33MHz)  
- 2CPU/2clocks(2.5V, 50/66MHz)  
-3IOAPICclocks(2.5V,16.67MHz)  
-4Fixedfrequency66MHzclocks(3.3V, 66MHz)  
-2REFclocks(3.3V,14.318MHz)  
Spread Spectrum may be enabled by driving the SPREAD#  
pin active. Spread spectrum typically reduces system EMI  
by 8dB to 10dB. This simplifies EMI qualification without  
resorting to board design iterations or costly shielding. The  
ICS9250-09 employs a proprietary closed loop design, which  
tightly controls the percentage of spreading over process  
and temperature variations.  
-1USBclock(3.3V,48MHz)  
•
•
•
Efficient power management through PD#, CPU_STOP#  
andPCI_STOP#.  
0.5% typical down spread modulation on CPU, PCI,  
IOAPIC, 3V66 and CPU/2 output clocks.  
Usesexternal14.318MHzcrystal.  
The CPU/2 clocks are inputs to the DRCG.  
Key Specification  
•
•
•
•
•
•
•
•
•
•
•
•
•
CPU Output Jitter: <250ps  
CPU/2 Output Jitter. <250ps  
IOAPIC Output Jitter: <500ps  
48MHz, 3V66, PCIOutputJitter:<500ps  
Ref Output Jitter. <1000ps  
Pin Configuration  
CPU Output Skew: <175ps  
CPU/2 Output Skew. <175ps  
IOAPIC Output Skew <250ps  
PCI Output Skew: <500ps  
3V66OutputSkew<250ps  
CPU to 3V66 Output Offset: 0.0 - 1.5ns (CPU leads)  
3V66 to PCI Output Offset: 1.5 - 4.0ns (3V66 leads)  
CPU to IOAPIC Output Offset 1.5 - 4.0ns (CPU leads)  
Block Diagram  
56-pin SSOP  
9250-09 Rev J 1/21/00  
ICS reserves the right to make changes in the device data identified in  
this publication without further notice. ICS advises its customers to  
obtain the latest version of all device data to verify that any  
information being relied upon by the customer is current and accurate.  

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