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ICS87931AYILF PDF预览

ICS87931AYILF

更新时间: 2024-09-30 14:51:23
品牌 Logo 应用领域
艾迪悌 - IDT 驱动逻辑集成电路
页数 文件大小 规格书
14页 156K
描述
PLL Based Clock Driver, 6 True Output(s), 0 Inverted Output(s), PQFP32, 7 X 7 MM, 1.40 MM HEIGHT, LQFP-32

ICS87931AYILF 技术参数

是否无铅:不含铅是否Rohs认证:符合
生命周期:Active零件包装代码:QFP
包装说明:LQFP,针数:32
Reach Compliance Code:compliantHTS代码:8542.39.00.01
风险等级:5.27Is Samacsys:N
输入调节:DIFFERENTIAL MUXJESD-30 代码:S-PQFP-G32
JESD-609代码:e3长度:7 mm
逻辑集成电路类型:PLL BASED CLOCK DRIVER湿度敏感等级:3
功能数量:1反相输出次数:
端子数量:32实输出次数:6
最高工作温度:85 °C最低工作温度:-40 °C
输出特性:3-STATE封装主体材料:PLASTIC/EPOXY
封装代码:LQFP封装形状:SQUARE
封装形式:FLATPACK, LOW PROFILE峰值回流温度(摄氏度):260
认证状态:Not QualifiedSame Edge Skew-Max(tskwd):0.6 ns
座面最大高度:1.6 mm最大供电电压 (Vsup):3.465 V
最小供电电压 (Vsup):3.135 V标称供电电压 (Vsup):3.3 V
表面贴装:YES温度等级:INDUSTRIAL
端子面层:MATTE TIN端子形式:GULL WING
端子节距:0.8 mm端子位置:QUAD
处于峰值回流温度下的最长时间:30宽度:7 mm
Base Number Matches:1

ICS87931AYILF 数据手册

 浏览型号ICS87931AYILF的Datasheet PDF文件第2页浏览型号ICS87931AYILF的Datasheet PDF文件第3页浏览型号ICS87931AYILF的Datasheet PDF文件第4页浏览型号ICS87931AYILF的Datasheet PDF文件第5页浏览型号ICS87931AYILF的Datasheet PDF文件第6页浏览型号ICS87931AYILF的Datasheet PDF文件第7页 
PRELIMINARY  
ICS87931I  
Integrated  
Circuit  
Systems, Incꢀ  
LOW SKEW, 1-TO-6  
LVCMOS/LVTTL CLOCK MULTIPLIER/ZERO DELAY BUFFER  
GENERAL DESCRIPTION  
FEATURES  
The ICS87931I is a low voltage, low skew  
Fully integrated PLL  
,&6  
LVCMOS/LVTTL Clock Multiplier/Zero Delay  
6 LVCMOS/LVTTL outputs, 7typical output impedance  
HiPerClockS™  
Buffer and a member of the HiPerClockS™ family  
of High Performance Clock Solutions from ICS.  
With output frequencies up to 150MHz, the  
Selectable differential CLK0, nCLK0 or LVCMOS/LVTTL clock  
for redundant clock applications  
ICS87931I is targeted for high performance clock applications.  
Along with a fully integrated PLL, the ICS87931I contains fre-  
quency configurable outputs and an external feedback input for  
regenerating clocks with “zero delay”.  
Maximum output frequency: 150MHz  
VCO range: 220MHz to 480MHz  
External feedback for “zero delay” clock regeneration  
Output skew, Same Frequency: 300ps (maximum)  
Output skew, Different Frequency: 400ps (maximum)  
Cycle-to-cycle jitter: ±100ps (typical)  
3.3V supply voltage  
Selectable clock inputs, CLK1 and differential CLK0, nCLK0  
support redundant clock applications. The CLK_SEL input de-  
termines which reference clock is used. The output divider val-  
ues of Bank A, B and C are controlled by the DIV_SELA,  
DIV_SELB and DIV_SELC, respectively.  
For test and system debug purposes, the PLL_SEL input al-  
lows the PLL to be bypassed. When LOW, the nMR input re-  
sets the internal dividers and forces the outputs to the high im-  
pedance state.  
-40°C to 85°C ambient operating temperature  
Pin compatible with MPC931  
The effective fanout of the ICS87931I can be increased to 12  
by utilizing the ability of each output to drive two series termi-  
nated transmission lines.  
PIN ASSIGNMENT  
32 31 30 29 28 27 26 25  
1
2
3
4
5
6
7
8
24  
23  
22  
21  
20  
19  
18  
17  
nc  
VDDA  
GND  
QB0  
POWER_DN  
CLK1  
QB1  
VDDO  
ICS87931I  
nMR  
EXTFB_SEL  
CLK_SEL  
PLL_SEL  
nc  
CLK0  
nCLK0  
GND  
9
10 11 12 13 14 15 16  
32-Lead LQFP  
7mm x 7mm x 1.4mm package body  
Y package  
Top View  
The Preliminary Information presented herein represents a product in prototyping or pre-production. The noted characteristics are based on initial  
product characterization. Integrated Circuit Systems, Incorporated (ICS) reserves the right to change any circuitry or specifications without notice.  
87931AYI  
www.icst.com/products/hiperclocks.html  
REV. A MARCH 14, 2003  
1

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