ICS8761
Integrated
Circuit
Systems, Inc.
LOW
V
OLTAGE, LOW
S
KEW
,
PCI / PCI-X CLOCK
GENERATOR
GENERAL DESCRIPTION
FEATURES
• Fully integrated PLL
The ICS8761 is a low voltage, low skew PCI /
ICS
PCI-X Clock Generator and a member of the
HiPerClockS™ family of High Performance Clock
Solutions from ICS.The ICS8761 has a selectable
REF_CLK or crystal input. The REF_CLK input
• 17 LVCMOS/LVTTL outputs, 15Ω typical output impedance
• Selectable crystal oscillator interface or
LVCMOS/LVTTL REF_CLK
HiPerClockS™
• Maximum output frequency: 166.67MHz
• Maximum crystal input frequency: 38MHz
• Maximum REF_CLK input frequency: 83.33MHz
• Individual banks with selectable output dividers for
generating 33.333MHz, 66.66MHz, 100MHz and
133.333MHz simultaneously
accepts LVCMOS or LVTTL input levels. The ICS8761 has a
fully integrated PLL along with frequency configurable clock
and feedback outputs for multiplying and regenerating clocks
with “zero delay”. Using a 20MHz or 25MHz crystal or a
33.333MHz or 66.666MHz reference frequency, the ICS8761
will generate output frequencies of 33.333MHz, 66.666MHz,
100MHz and 133.333MHz simultaneously.
• Separate feedback control for generating PCI / PCI-X
frequencies from a 20MHz or 25MHz crystal or 33.333MHz
or 66.666MHz reference frequency
The low impedance LVCMOS/LVTTL outputs of the ICS8761
are designed to drive 50Ω series or parallel terminated
transmission lines.
• Cycle-to-cycle jitter: 70ps (maximum)
• Period jitter, RMS: 17ps (maximum)
• Output skew: 230ps (maximum)
• Bank skew: 40ps (maximum)
• Static phase offset: 0 150ps (maximum)
• Full 3.3V or 3.3V core, 2.5V multiple output supply modes
• 0°C to 85°C ambient operating temperature
• Lead-Free package available
BLOCK DIAGRAM
OEA
MR
D_SELA0
D_SELA1
QA0
QA1
PIN ASSIGNMENT
REF_CLK
XTAL1
0 0
0 1
1 0
1 1
0
1
÷3
÷4
QA2
QA3
0
1
÷6
OSC
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
÷12
XTAL2
PLL
1
2
3
4
5
6
7
8
48
47
46
45
44
43
42
41
G
ND
REF_CLK
GND
QB0
QB1
QB2
QB3
XTAL_SEL
FB_IN
FB_OUT
0 0
0 1
1 0
1 1
V
DDOFB
XTAL1
XTAL2
PLL_SEL
OEB
FB_IN
V
DD
V
DD
FBDIV_SEL0
FBDIV_SEL1
MR
D_SELB1
D_SELB0
XTAL_SEL
PLL_SEL
QC0
QC1
QC2
QC3
0 0
0 1
1 0
1 1
V
DDA
DD
ICS8761
OEC
V
DD
V
9
40
39
38
37
36
35
34
33
D_SELC0
D_SELD0
10
11
12
13
14
15
16
D_SELC1
OEC
D_SELD1
OED
D_SELC1
D_SELC0
OEA
OEB
QD0
QD1
OED
0 0
0 1
1 0
1 1
D_SELA0
D_SELA1
GND
D_SELB0
D_SELB1
GND
QD2
QD3
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
D_SELD1
D_SELD0
÷6
÷12
÷16
÷20
0 0
0 1
1 0
1 1
64-Lead LQFP
10mm x 10mm x 1.4mm package body
Y package
FB_OUT
TopView
FBDIV_SEL1
FBDIV_SEL0
8761CY
www.icst.com/products/hiperclocks.html
REV. C SEPTEMBER 7, 2004
1