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ICS8761CYILF PDF预览

ICS8761CYILF

更新时间: 2024-09-30 14:51:23
品牌 Logo 应用领域
艾迪悌 - IDT 时钟外围集成电路晶体
页数 文件大小 规格书
16页 280K
描述
Processor Specific Clock Generator, 166.67MHz, CMOS, PQFP64, 10 X 10 MM, 1.40 MM HEIGHT, ROHS COMPLIANT, MS-026BCD, LQFP-64

ICS8761CYILF 技术参数

是否无铅:不含铅是否Rohs认证:符合
生命周期:Obsolete零件包装代码:QFP
包装说明:LFQFP, QFP64,.47SQ,20针数:64
Reach Compliance Code:compliantECCN代码:EAR99
HTS代码:8542.39.00.01风险等级:5.8
Is Samacsys:NJESD-30 代码:S-PQFP-G64
JESD-609代码:e3长度:10 mm
湿度敏感等级:3端子数量:64
最高工作温度:85 °C最低工作温度:-40 °C
最大输出时钟频率:166.67 MHz封装主体材料:PLASTIC/EPOXY
封装代码:LFQFP封装等效代码:QFP64,.47SQ,20
封装形状:SQUARE封装形式:FLATPACK, LOW PROFILE, FINE PITCH
峰值回流温度(摄氏度):260电源:2.5/3.3,3.3 V
主时钟/晶体标称频率:83.33 MHz认证状态:Not Qualified
座面最大高度:1.6 mm子类别:Clock Generators
最大供电电压:3.465 V最小供电电压:3.135 V
标称供电电压:3.3 V表面贴装:YES
技术:CMOS温度等级:INDUSTRIAL
端子面层:Matte Tin (Sn) - annealed端子形式:GULL WING
端子节距:0.5 mm端子位置:QUAD
处于峰值回流温度下的最长时间:30宽度:10 mm
uPs/uCs/外围集成电路类型:CLOCK GENERATOR, PROCESSOR SPECIFICBase Number Matches:1

ICS8761CYILF 数据手册

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ICS8761I  
LOW VOLTAGE, LOW SKEW,  
PCI / PCI-X CLOCK GENERATOR  
GENERAL DESCRIPTION  
FEATURES  
Fully integrated PLL  
The ICS8761I is a low voltage, low skew PCI / PCI-X clock  
generator. The ICS8761I has a selectable REF_CLK or  
crystal input. The REF_CLK input accepts LVCMOS or LVTTL  
input levels. The ICS8761I has a fully integrated PLL along  
with frequency configurable clock and feedback outputs for  
multiplying and regenerating clocks with “zero delay”. Using  
a 20MHz or 25MHz crystal or a 33.333MHz or 66.666MHz  
reference frequency, the ICS8761I will generate output  
frequencies of 33.333MHz, 66.666MHz, 100MHz and  
133.333MHz simultaneously.  
Seventeen LVCMOS/LVTTL outputs,  
15Ω typical output impedance  
Selectable crystal oscillator interface  
or LVCMOS/LVTTL REF_CLK  
Maximum output frequency: 166.67MHz  
Maximum crystal input frequency: 40MHz  
Maximum REF_CLK input frequency: 83.33MHz  
Individual banks with selectable output dividers  
for generating 33.333MHz, 66.66MHz, 100MHz  
and 133.333MHz simultaneously  
The low impedance LVCMOS/LVTTL outputs of the ICS8761I  
are designed to drive 50Ω series or parallel terminated  
transmission lines.  
Separate feedback control for generating PCI / PCI-X  
frequencies from a 20MHz or 25MHz crystal or 33.333MHz  
or 66.666MHz reference frequency  
Cycle-to-cycle jitter: 70ps (maximum)  
Period jitter, RMS: 17ps (maximum)  
Output skew: 250ps (maximum)  
Bank skew: 50ps (maximum)  
Static phase offset: 0 150ps (maximum)  
Full 3.3V or 3.3V core, 2.5V multiple output supply modes  
-40°C to 85°C ambient operating temperature  
Available in both standard and lead-free RoHS-compliant  
packages  
BLOCK DIAGRAM  
OEA  
MR  
D_SELA0  
D_SELA1  
QA0  
QA1  
PIN ASSIGNMENT  
REF_CLK  
XTAL1  
0 0  
0 1  
1 0  
1 1  
0
1
÷3  
÷4  
QA2  
QA3  
0
1
÷6  
OSC  
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49  
÷12  
XTAL2  
PLL  
1
2
3
4
5
6
7
8
48  
47  
46  
45  
44  
43  
42  
41  
GND  
REF_CLK  
GND  
QB0  
QB1  
QB2  
QB3  
XTAL_SEL  
FB_IN  
FB_OUT  
VDDOFB  
0 0  
0 1  
1 0  
1 1  
XTAL1  
PLL_SEL  
OEB  
FB_IN  
XTAL2  
VDD  
VDD  
FBDIV_SEL0  
FBDIV_SEL1  
D_SELB1  
D_SELB0  
XTAL_SEL  
PLL_SEL  
QC0  
QC1  
QC2  
QC3  
0 0  
0 1  
1 0  
1 1  
MR  
VDDA  
VDD  
ICS8761I  
OEC  
VDD  
9
40  
39  
38  
37  
36  
35  
34  
33  
D_SELC0  
D_SELD0  
10  
11  
12  
13  
14  
15  
16  
D_SELC1  
OEC  
D_SELD1  
OED  
D_SELC1  
D_SELC0  
OEA  
OEB  
QD0  
QD1  
OED  
0 0  
0 1  
1 0  
1 1  
D_SELA0  
D_SELA1  
GND  
D_SELB0  
D_SELB1  
GND  
QD2  
QD3  
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32  
D_SELD1  
D_SELD0  
÷6  
÷12  
÷16  
÷20  
0 0  
0 1  
1 0  
1 1  
64-Lead LQFP  
10mm x 10mm x 1.4mm package body  
Y package  
FB_OUT  
Top View  
FBDIV_SEL1  
FBDIV_SEL0  
8761CYI  
www.idt.com  
REV. C JULY 27, 2010  
1

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