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ICS87604GILF PDF预览

ICS87604GILF

更新时间： 2024-09-30 21:00:39
品牌 Logo 应用领域
艾迪悌 - IDT 光电二极管
页数 文件大小 规格书
11页 155K
描述
Clock Generator, PDSO28

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中文翻译

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ICS87604GILF 技术参数

是否Rohs认证： 符合生命周期：Obsolete
Reach Compliance Code：unknown风险等级：5.84
JESD-30 代码：R-PDSO-G28JESD-609代码：e3
湿度敏感等级：3端子数量：28
最高工作温度：85 °C最低工作温度：-40 °C
封装主体材料：PLASTIC/EPOXY封装代码：TSSOP
封装等效代码：TSSOP28,.3封装形状：RECTANGULAR
封装形式：SMALL OUTLINE, THIN PROFILE, SHRINK PITCH电源：3.3 V
认证状态：Not Qualified子类别：Clock Generators
最大压摆率：185 mA标称供电电压：3.3 V
表面贴装：YES温度等级：INDUSTRIAL
端子面层：Matte Tin (Sn) - annealed端子形式：GULL WING
端子节距：0.635 mm端子位置：DUAL
Base Number Matches：1

ICS87604GILF 数据手册

 浏览型号ICS87604GILF的Datasheet PDF文件第2页浏览型号ICS87604GILF的Datasheet PDF文件第3页浏览型号ICS87604GILF的Datasheet PDF文件第4页浏览型号ICS87604GILF的Datasheet PDF文件第5页浏览型号ICS87604GILF的Datasheet PDF文件第6页浏览型号ICS87604GILF的Datasheet PDF文件第7页 
ICS87604I  
LOW VOLTAGE/LOW SKEW, 1:4 PCI/PCI-X  
ZERO DELAY CLOCK GENERATOR  
Integrated  
Circuit  
Systems, Inc.  
GENERAL DESCRIPTION  
FEATURES  
• Fully integrated PLL  
The ICS87604I is a 1:4 PCI/PCI-X Clock  
ICS  
Generator and a member of the HiPerClockSTM  
family of high performance clock solutions from  
ICS.The ICS87604I has a selectable REF_CLK  
or crystal input. The REF_CLK input accepts  
• 4 LVCMOS/LVTTL outputs, 15Ω typical output impedance  
HiPerClockS™  
• Selectable crystal oscillator interface or  
LVCMOS/LVTTL REF_IN clock input  
LVCMOS or LVTTL input levels. The ICS87604I has a fully  
integrated PLL along with frequency configurable clock and  
feedback outputs for multiplying and regenerating clocks with  
“zero delay”. The PLL’s VCO has an operating range of  
250MHz-500MHz, allowing this device to be used in a variety  
of general purpose clocking applications. For PCI/PCI-X  
applications in particular, the VCO frequency should be set to  
400MHz.This can be accomplished by supplying 33.33MHz,  
25MHz, 20MHz, or 16.66MHz on the reference clock or crystal  
input and by selecting ÷12, ÷16, ÷20, or ÷24, respectively as  
the feedback divide value.The divider on the output bank can  
then be configured to generate 33.33MHz (÷12), 66.66MHz  
(÷6), 100MHz (÷4), or 133.33MHz (÷3).  
• Maximum output frequency: 166.67MHz  
• Maximum crystal input frequency: 38MHz  
• Maximum REF_IN input frequency: 41.67MHz  
• Individual banks with selectable output dividers for  
generating 33.333MHz, 66.66MHz, 100MHz and  
133.333MHz  
• Separate feedback control for generating PCI / PCI-X  
frequencies from a 16.66MHz or 20MHz crystal, or 25MHz  
or 33.33MHz reference frequency  
• VCO range: 250MHz to 500MHz  
• Cycle-to-cycle jitter: 120ps (maximum)  
• Period jitter, RMS: 20ps (maximum)  
• Output skew: 65ps (maximum)  
The ICS87604I is characterized to operate with its core supply  
at 3.3V and the bank supply at 3.3V or 2.5V.The ICS87604I is  
packaged in a small 6.1mm x 9.7mm TSSOP body, making it  
ideal for use in space-constrained applications.  
• Static phase offset: 160ps 160ps  
• Voltage Supply Modes:  
VDD/VDDA/VDDO  
3.3/3.3/3.3  
3.3/3.3/2.5  
• -40°C to 85°C ambient operating temperature  
• Lead-Free package fully RoHS compliant  
BLOCK DIAGRAM  
DIV_SEL0  
DIV_SEL1  
PIN ASSIGNMENT  
XTAL_SEL  
1
2
3
4
VDD  
FB_IN  
GND  
28  
27  
26  
25  
FBDIV_SEL1  
FBDIV_SEL0  
DIV_SEL1  
Q0  
Q1  
Q2  
Q3  
0
0
1
0
1
0
÷3  
÷4  
REF_IN  
FB_OUT  
REF_OUT  
VDDO  
DIV_SEL0  
nc  
0
1
0
1
24  
23  
22  
21  
20  
19  
5
6
7
8
XTAL_IN  
÷6  
MR  
nc  
OSC  
÷12  
1
1
Q3  
XTAL_OUT  
PLL  
Q2  
GND  
GND  
nc  
GND  
Q1  
Q0  
9
FB_IN  
10  
11  
12  
13  
18  
17  
16  
15  
REF_IN  
XTAL_OUT  
XTAL_IN  
VDDO  
PLL_SEL  
VDDA  
÷12  
÷16  
÷20  
0
0
1
0
1
0
PLL_SEL  
REF_OUT  
FB_OUT  
14  
XTAL_SEL  
÷24  
1
1
ICS87604I  
28-Lead TSSOP, 240-MIL  
6.1mm x 9.7mm x 0.92mm  
body package  
FBDIV_SEL1  
FBDIV_SEL0  
MR  
G Package  
TopView  
87604AGI  
www.icst.com/products/hiperclocks.html  
REV. A APRIL 12, 2005  
1
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