ICS87608I
LOW VOLTAGE/LOW SKEW, 1:8 PCI/PCI-X
ZERO DELAY CLOCK GENERATOR
Integrated
Circuit
Systems, Inc.
GENERAL DESCRIPTION
FEATURES
• Fully integrated PLL
The ICS87608I has a selectable REF_CLK or
ICS
crystal input. The REF_CLK input accepts
LVCMOS or LVTTL input levels. The ICS87608I
has a fully integrated PLL along with frequency
configurable clock and feedback outputs for
• 8 LVCMOS/LVTTL outputs, 15Ω typical output impedance
HiPerClockS™
• Selectable crystal oscillator interface or
LVCMOS/LVTTL REF_IN clock input
multiplying and regenerating clocks with “zero delay”.
• Maximum output frequency: 166.67MHz
• Maximum crystal input frequency: 38MHz
• Maximum REF_IN input frequency: 41.67MHz
The ICS87608I is a 1:8 PCI/PCI-X Clock Generator and a
member of the HiPerClockSTM family of high performance clock
solutions from ICS.The ICS87608I has a selectable REF_CLK
or crystal input. The REF_CLK input accepts LVCMOS or
LVTTL input levels.The ICS87608I has a fully integrated PLL
along with frequency configurable clock and feedback outputs
for multiplying and regenerating clocks with “zero delay”.The
PLL’s VCO has an operating range of 250MHz-500MHz,
allowing this device to be used in a variety of general purpose
clocking applications. For PCI/PCI-X applications in particular,
the VCO frequency should be set to 400MHz. This can be
accomplished by supplying 33.33MHz, 25MHz, 20MHz, or
16.66MHz on the reference clock or crystal input and by
selecting ÷12, ÷16, ÷20, or ÷24, respectively as the feedback
divide value. The dividers on each of the two output banks
can then be independently configured to generate 33.33MHz
(÷12), 66.66MHz (÷6), 100MHz (÷4), or 133.33MHz (÷3).
• Individual banks with selectable output dividers for
generating 33.333MHz, 66.66MHz, 100MHz and
133.333MHz
• Separate feedback control for generating PCI / PCI-X
frequencies from a 16.66MHz or 20MHz crystal, or 25MHz
or 33.33MHz reference frequency
• VCO range: 200MHz to 500MHz
• Cycle-to-cycle jitter: 120ps (maximum), @ 3.3V
• Period jitter, RMS: 20ps (maximum)
• Output skew: 250ps (maximum)
• Bank skew: 60ps (maximum)
• Static phase offset: 160ps 160ps
• Voltage Supply Modes:
VDD (core/inputs), VDDA (analog supply for PLL),
VDDOA (output bank A),
The ICS87608I is characterized to operate with its core supply
at 3.3V and each bank supply at 3.3V or 2.5V.The ICS87608I
is packaged in a small 7x7mm body LQFP, making it ideal for
use in space-constrained applications.
VDDOB (output bank B, REF_OUT, FB_OUT)
VDD/VDDA/VDDOA/VDDOB
3.3/3.3/3.3/3.3
3.3/3.3/2.5/3.3
3.3/3.3/3.3/2.5
3.3/3.3/2.5/2.5
PIN ASSIGNMENT
• Lead-Free package fully RoHS compliant
• -40°C to 85°C ambient operating temperature
32 31 30 29 28 27 26 25
QA0
QA1
1
2
3
4
5
6
7
8
24
23
22
21
20
19
18
17
QB0
QB1
ICS87608I
GND
GND
32-Lead LQFP
7mm x 7mm x 1.4mm
package body
QA2
QB2
QA3
QB3
VDDOA
VDDOB
REF_OUT
FB_OUT
Y package
TopView
MR
DIV_SELA0
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87608AYI
www.icst.com/products/hiperclocks.html
REV. B MARCH 11, 2005
1