ICS8752I

更新时间： 2024-09-30 12:20:39

品牌	Logo	应用领域
艾迪悌 - IDT		时钟
页数	文件大小	规格书
14页	118K
描述
LOW SKEW, 1-TO-8 LVCMOS CLOCK MULTIPLIER/ZERO DELAY BUFFER

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ICS8752I 数据手册

ICS8752I

LOW SKEW, 1-TO-8

LVCMOS CLOCK MULTIPLIER/ZERO DELAY BUFFER

GENERAL DESCRIPTION

FEATURES

The ICS8752I is a low voltage, low skew LVCMOS clock

generator. With output up to 240MHz, the ICS8752I is

targeted for high performance clock applications. Along with

a fully integrated PLL, the ICS8752I contains frequency

configurable outputs and an external feedback input for

regenerating clocks with “zero delay”.

• Fully integrated PLL

• 8 LVCMOS outputs, 7Ω typical output impedance

• Selectable LVCMOS CLK0 or CLK1 inputs for

redundant clock applications

• Input/Output frequency range: 18.33MHz to 240MHz

at V_CC= 3.3V 5ꢀ

Dual clock inputs, CLK0 and CLK1, support redundant clock

applications. The CLK_SEL input determines which reference

clock is used. The output divider values of Bank A and B are

controlled by the DIV_SELA0:1, and DIV_SELB0:1, respectively.

• VCO range: 220MHz to 480MHz

• External feedback for “zero delay” clock regeneration

For test and system debug purposes, the PLL_SEL input

allows the PLL to be bypassed. When HIGH, the MR/nOE

input resets the internal dividers and forces the outputs to

the high impedance state.

• Cycle-to-cycle jitter: 75ps (maximum),

(all outputs are the same frequency)

• Output skew: 100ps (maximum)

• Bank skew: 55ps (maximum)

The low impedance LVCMOS outputs of the ICS8752I are

designed to drive terminated transmission lines. The

effective fanout of each output can be doubled by

utilizing the ability of each output to drive two series

terminated transmission lines.

• Full 3.3V or 2.5V supply voltage

• -40°C to 85°C ambient operating temperature

• Lead-Free package fully RoHS compliant

BLOCK DIAGRAM

PIN ASSIGNMENT

PLL_SEL

PLL

FB_IN

PHASE

÷2

÷4

VCO

CLK0

32 31 30 29 28 27 26 25

DETECTOR

CLK1

QA0

QA1

QA2

QA3

÷6

DIV_SELB0

DIV_SELB1

DIV_SELA0

DIV_SELA1

MR/nOE

CLK0

GND

QB1

QB0

V^DDO

VDDO

QA3

QA2

GND

CLK_SEL

÷8

÷12

DIV_SELA1

DIV_SELA0

ICS8752I

QB0

QB1

QB2

QB3

GND

FB_IN

DIV_SELB1

DIV_SELB0

10 11 12 13 14 15 16

32-Lead LQFP

7mm x 7mm x 1.4mm package body

Y package

TopView

MR/nOE

8752CYI

www.idt.com

REV.C JULY 30, 2010

12 3 4 5 6 7...14

中文翻译

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与ICS8752I相关器件

型号	品牌	获取价格	描述	数据表
ICS8752YLF	IDT	获取价格	Low Skew Clock Driver, 8 True Output(s), 0 Inverted Output(s), CMOS, PQFP32, 7 X 7 MM, 1.4
ICS87604AGI	IDT	获取价格	Processor Specific Clock Generator, 166.67MHz, PDSO28, 6.10 X 9.70 MM, 0.92 MM HEIGHT, MO-
ICS87604AGILF	IDT	获取价格	Processor Specific Clock Generator, 166.67MHz, PDSO28, 6.10 X 9.70 MM, 0.92 MM HEIGHT, LEA
ICS87604GILF	IDT	获取价格	Clock Generator, PDSO28
ICS87604GILFT	IDT	获取价格	Clock Generator, PDSO28
ICS87608AYI	ETC	获取价格	LOW VOLTAGE/LOW SKEW, 1:8 PCI/PCI-X ZERO DELAY CLOCK GENERATOR
ICS87608AYILF	ETC	获取价格	LOW VOLTAGE/LOW SKEW, 1:8 PCI/PCI-X ZERO DELAY CLOCK GENERATOR
ICS87608AYILFT	ETC	获取价格	LOW VOLTAGE/LOW SKEW, 1:8 PCI/PCI-X ZERO DELAY CLOCK GENERATOR
ICS87608AYIT	ETC	获取价格	LOW VOLTAGE/LOW SKEW, 1:8 PCI/PCI-X ZERO DELAY CLOCK GENERATOR
ICS87608I	ETC	获取价格	LOW VOLTAGE/LOW SKEW, 1:8 PCI/PCI-X ZERO DELAY CLOCK GENERATOR

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