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ICS8752CYLFT PDF预览

ICS8752CYLFT

更新时间: 2024-09-30 13:08:35
品牌 Logo 应用领域
艾迪悌 - IDT 时钟
页数 文件大小 规格书
14页 136K
描述
PLL Based Clock Driver, 8752 Series, 8 True Output(s), 0 Inverted Output(s), PQFP32, 7 X 7 MM, 1.40 MM HEIGHT, ROHS COMPLIANT, MS-026, LQFP-32

ICS8752CYLFT 技术参数

是否无铅: 不含铅是否Rohs认证: 符合
生命周期:Obsolete零件包装代码:QFP
包装说明:LQFP, QFP32,.35SQ,32针数:32
Reach Compliance Code:unknownHTS代码:8542.39.00.01
风险等级:5.81其他特性:ALSO OPERATES AT 3.3V SUPPLY
系列:8752输入调节:MUX
JESD-30 代码:S-PQFP-G32JESD-609代码:e3
长度:7 mm逻辑集成电路类型:PLL BASED CLOCK DRIVER
湿度敏感等级:3功能数量:1
反相输出次数:端子数量:32
实输出次数:8最高工作温度:70 °C
最低工作温度:封装主体材料:PLASTIC/EPOXY
封装代码:LQFP封装等效代码:QFP32,.35SQ,32
封装形状:SQUARE封装形式:FLATPACK, LOW PROFILE
峰值回流温度(摄氏度):260电源:2.5/3.3 V
认证状态:Not QualifiedSame Edge Skew-Max(tskwd):0.09 ns
座面最大高度:1.6 mm子类别:Clock Drivers
最大供电电压 (Vsup):2.625 V最小供电电压 (Vsup):2.375 V
标称供电电压 (Vsup):2.5 V表面贴装:YES
技术:CMOS温度等级:COMMERCIAL
端子面层:Matte Tin (Sn) - annealed端子形式:GULL WING
端子节距:0.8 mm端子位置:QUAD
处于峰值回流温度下的最长时间:30宽度:7 mm
最小 fmax:240 MHzBase Number Matches:1

ICS8752CYLFT 数据手册

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ICS8752  
LOW SKEW, 1-TO-8  
LVCMOS CLOCK MULTIPLIER/ZERO DELAY BUFFER  
GENERAL DESCRIPTION  
FEATURES  
The ICS8752 is a low voltage, low skew LVCMOS clock  
generator. With output frequencies up to 240MHz, the  
ICS8752 is targeted for high performance clock applcations.  
Along with a fully integrated PLL, the ICS8752 contains  
frequency configurable outputs and an external feedback  
input for regenerating clocks with “zero delay”.  
Fully integrated PLL  
Eight LVCMOS outputs, 7Ω typical output impedance  
Selectable LVCMOS CLK0 or CLK1 inputs for  
redundant clock applications  
Input/Output frequency range: 18.33MHz to 240MHz  
at VCC = 3.3V 5ꢀ  
Dual clock inputs, CLK0 and CLK1, support redundant clock  
applications. The CLK_SEL input determines which refer-  
ence clock is used. The output divider values of Bank A and  
B are controlled by the DIV_SELA0:1, and DIV_SELB0:1,  
respectively.  
VCO range: 220MHz to 480MHz  
External feedback for “zero delay” clock regeneration  
Cycle-to-cycle jitter: 75ps (maximum),  
(all outputs are the same frequency)  
For test and system debug purposes, the PLL_SEL input  
allows the PLL to be bypassed. When HIGH, the MR/nOE  
input resets the internal dividers and forces the outputs to  
the high impedance state.  
Output skew: 100ps (maximum)  
Bank skew: 55ps (maximum)  
The low impedance LVCMOS outputs of the ICS8752 are  
designed to drive terminated transmission lines. The  
effective fanout of each output can be doubled by  
utilizing the ability of each output to drive two series  
terminated transmission lines.  
Full 3.3V or 2.5V supply voltage  
0°C to 70°C ambient operating temperature  
Available in both standard and lead-free RoHS-compliant  
packages  
BLOCK DIAGRAM  
PIN ASSIGNMENT  
PLL_SEL  
PLL  
FB_IN  
PHASE  
÷2  
÷4  
00  
01  
10  
11  
VCO  
CLK0  
0
32 31 30 29 28 27 26 25  
DETECTOR  
1
0
CLK1  
QA0  
QA1  
QA2  
QA3  
1
÷6  
DIV_SELB0  
DIV_SELB1  
DIV_SELA0  
DIV_SELA1  
MR/nOE  
CLK0  
1
2
3
4
5
6
7
8
24  
23  
22  
21  
20  
19  
18  
17  
GND  
QB1  
QB0  
VDDO  
VDDO  
QA3  
QA2  
GND  
CLK_SEL  
÷8  
÷12  
DIV_SELA1  
DIV_SELA0  
ICS8752  
00  
01  
10  
11  
QB0  
QB1  
QB2  
QB3  
GND  
FB_IN  
DIV_SELB1  
DIV_SELB0  
9
10 11 12 13 14 15 16  
32-Lead LQFP  
7mm x 7mm x 1.4mm package body  
Y package  
TopView  
MR/nOE  
8752CY  
www.idt.com  
REV. C JULY 2, 2010  
1

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