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ICS8531AY-01LFT PDF预览

ICS8531AY-01LFT

更新时间: 2024-11-05 14:51:23
品牌 Logo 应用领域
艾迪悌 - IDT 驱动逻辑集成电路
页数 文件大小 规格书
18页 294K
描述
Low Skew Clock Driver, 8531 Series, 9 True Output(s), 0 Inverted Output(s), PQFP32, 7 X 7 MM, 1.40 MM HEIGHT, ROHS COMPLIANT, MS-026BBA, LQFP-32

ICS8531AY-01LFT 技术参数

是否无铅: 不含铅是否Rohs认证: 符合
生命周期:End Of Life零件包装代码:QFP
包装说明:7 X 7 MM, 1.40 MM HEIGHT, ROHS COMPLIANT, MS-026BBA, LQFP-32针数:32
Reach Compliance Code:compliantECCN代码:EAR99
HTS代码:8542.39.00.01风险等级:5.15
系列:8531输入调节:DIFFERENTIAL MUX
JESD-30 代码:S-PQFP-G32JESD-609代码:e3
长度:7 mm逻辑集成电路类型:LOW SKEW CLOCK DRIVER
湿度敏感等级:3功能数量:1
反相输出次数:端子数量:32
实输出次数:9最高工作温度:70 °C
最低工作温度:封装主体材料:PLASTIC/EPOXY
封装代码:LQFP封装等效代码:QFP32,.35SQ,32
封装形状:SQUARE封装形式:FLATPACK, LOW PROFILE
峰值回流温度(摄氏度):260电源:3.3 V
Prop。Delay @ Nom-Sup:2 ns传播延迟(tpd):2 ns
认证状态:Not QualifiedSame Edge Skew-Max(tskwd):0.05 ns
座面最大高度:1.6 mm子类别:Clock Drivers
最大供电电压 (Vsup):3.465 V最小供电电压 (Vsup):3.135 V
标称供电电压 (Vsup):3.3 V表面贴装:YES
温度等级:COMMERCIAL端子面层:Matte Tin (Sn) - annealed
端子形式:GULL WING端子节距:0.8 mm
端子位置:QUAD处于峰值回流温度下的最长时间:30
宽度:7 mmBase Number Matches:1

ICS8531AY-01LFT 数据手册

 浏览型号ICS8531AY-01LFT的Datasheet PDF文件第2页浏览型号ICS8531AY-01LFT的Datasheet PDF文件第3页浏览型号ICS8531AY-01LFT的Datasheet PDF文件第4页浏览型号ICS8531AY-01LFT的Datasheet PDF文件第5页浏览型号ICS8531AY-01LFT的Datasheet PDF文件第6页浏览型号ICS8531AY-01LFT的Datasheet PDF文件第7页 
LOW SKEW, 1-TO-9, DIFFERENTIAL-TO-  
3.3V LVPECL FANOUT BUFFER  
ICS8531-01  
GENERAL DESCRIPTION  
FEATURES  
The ICS8531-01 is a low skew, high performance  
Nine differential 3.3V LVPECL outputs  
ICS  
HiPerClockS™  
1-to-9 Differential-to-3.3V LVPECL Fanout Buffe  
Selectable differential CLK, nCLK or LVPECL clock inputs  
and a member of the HiPerClockS™ family of High  
Performance Clock Solutions from IDT. The  
ICS8531-01 has two selectable clock inputs. The  
CLK, nCLK pair can accept the following differential  
input levels: LVPECL, LVDS, LVHSTL, SSTL, HCSL  
CLK, nCLK pair can accept most standard differential input  
levels. The PCLK, nPCLK pair can accept LVPECL, CML, or  
SSTL input levels. The clock enable is internally synchronized  
to eliminate runt pulses on the outputs during asynchronous  
assertion/deassertion of the clock enable pin.  
PCLK, nPCLK supports the following input types:  
LVPECL, CML, SSTL  
Maximum output frequency: 500MHz  
Translates any single ended input signal (LVCMOS, LVTTL,  
GTL) to 3.3V LVPECL levels with resistor bias on nCLK input  
Guaranteed output skew and part-to-part skew character-  
istics make the ICS8531-01 ideal for high performance work-  
station and server applications.  
Additive phase jitter, RMS: 0.17ps (typical)  
Output skew: 50ps (maximum)  
Part-to-part skew: 250ps (maximum)  
Propagation delay: 2ns (maximum)  
3.3V operating supply  
0°C to 70°C ambient operating temperature  
Available in both standard (RoHS 5) and lead-free (RoHS 6)  
packages  
Industrial Temperature information available upon request  
BLOCK DIAGRAM  
PIN ASSIGNMENT  
D
CLK_EN  
Q
32 31 30 29 28 27 26 25  
LE  
CLK  
nCLK  
PCLK  
0
1
VCC  
CLK  
1
2
3
4
5
6
7
8
24  
23  
22  
21  
20  
19  
18  
17  
VCCO  
Q3  
Q0  
nQ0  
nPCLK  
nCLK  
nQ3  
Q4  
Q1  
nQ1  
CLK_SEL  
PCLK  
CLK_SEL  
ICS8531-01  
nQ4  
Q5  
Q2  
nQ2  
nPCLK  
VEE  
nQ5  
VCCO  
Q3  
nQ3  
CLK_EN  
9 10 11 12 13 14 15 16  
Q4  
nQ4  
Q5  
nQ5  
32-Lead LQFP  
7mm x 7mm x 1.4mm package body  
Q6  
nQ6  
Y package  
Top View  
Q7  
nQ7  
Q8  
nQ8  
IDT/ ICS1-TO-9, 3.3V LVPECL FANOUT BUFFER  
1
ICS8531AY-01 REV. F APRIL 11, 2007  

ICS8531AY-01LFT 替代型号

型号 品牌 替代类型 描述 数据表
8531AY-01LFT IDT

功能相似

Low Skew, 1-to-9, Different ial-to-3.3V LVPECL Fanout Buffer
8531AY-01LF IDT

功能相似

Low Skew, 1-to-9, Different ial-to-3.3V LVPECL Fanout Buffer

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