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ICS853210BYT PDF预览

ICS853210BYT

更新时间: 2024-11-05 15:34:35
品牌 Logo 应用领域
艾迪悌 - IDT 驱动逻辑集成电路
页数 文件大小 规格书
10页 132K
描述
Low Skew Clock Driver, 5 True Output(s), 0 Inverted Output(s), PQFP32, 7 X 7 MM, 1.40 MM HEIGHT, LQFP-32

ICS853210BYT 技术参数

是否无铅: 含铅是否Rohs认证: 不符合
生命周期:Obsolete零件包装代码:QFP
包装说明:LQFP,针数:32
Reach Compliance Code:compliantHTS代码:8542.39.00.01
风险等级:5.92其他特性:ECL MODE: VCC=0V WITH VEE=-2.375 TO -3.8V
输入调节:DIFFERENTIALJESD-30 代码:S-PQFP-G32
JESD-609代码:e0长度:7 mm
逻辑集成电路类型:LOW SKEW CLOCK DRIVER湿度敏感等级:3
功能数量:2反相输出次数:
端子数量:32实输出次数:5
最高工作温度:85 °C最低工作温度:-40 °C
封装主体材料:PLASTIC/EPOXY封装代码:LQFP
封装形状:SQUARE封装形式:FLATPACK, LOW PROFILE
峰值回流温度(摄氏度):240认证状态:Not Qualified
座面最大高度:1.6 mm最大供电电压 (Vsup):3.8 V
最小供电电压 (Vsup):2.375 V标称供电电压 (Vsup):3.3 V
表面贴装:YES温度等级:INDUSTRIAL
端子面层:Tin/Lead (Sn/Pb)端子形式:GULL WING
端子节距:0.8 mm端子位置:QUAD
处于峰值回流温度下的最长时间:20宽度:7 mm
Base Number Matches:1

ICS853210BYT 数据手册

 浏览型号ICS853210BYT的Datasheet PDF文件第2页浏览型号ICS853210BYT的Datasheet PDF文件第3页浏览型号ICS853210BYT的Datasheet PDF文件第4页浏览型号ICS853210BYT的Datasheet PDF文件第5页浏览型号ICS853210BYT的Datasheet PDF文件第6页浏览型号ICS853210BYT的Datasheet PDF文件第7页 
PRELIMINARY  
ICS853210  
Integrated  
Circuit  
Systems, Incꢀ  
LOW SKEW, DUAL, 1-TO-5  
DIFFERENTIAL-TO-2.5V/3.3V LVPECL/ECL FANOUT BUFFER  
GENERAL DESCRIPTION  
FEATURES  
The ICS853210 is a low skew, high perfor- 2 differential 2.5V/3.3V LVPECL/ ECL bank outputs  
mance dual 1-to-5 Differential-to-2.5V/3.3V  
LVPECL/ECL Fanout Buffer and a member of  
2 differential clock input pairs  
HiPerClockS™  
the HiPerClockS™ family of High Performance  
Clock Solutions from ICS. The ICS853210  
PCLKx, nPCLKx pairs can accept the following  
differential input levels: LVPECL, LVDS, CML, SSTL  
is characterized to operate from either a 2.5V or a 3.3V  
power supply. Guaranteed output and part-to-part skew  
characteristics make the ICS853210 ideal for those clock  
distribution applications demanding well defined perfor-  
mance and repeatability.  
Maximum output frequency: >3GHz  
Translates any single ended input signal to 3.3V  
LVPECL levels with resistor bias on nPCLKx input  
Output skew: 20ps (typical)  
Part-to-part skew: 85ps (typical)  
Propagation delay: TBD  
LVPECL mode operating voltage supply range:  
VCC = 2.375V to 3.8V, VEE = 0V  
ECL mode operating voltage supply range:  
VCC = 0V, VEE = -2.375V to -3.8V  
-40°C to 85°C ambient operating temperature  
Pin compatible with MC100EP210 and MC100LVEP210  
BLOCK DIAGRAM  
PIN ASSIGNMENT  
QA0  
nQA0  
PCLKA  
nPCLKA  
QA1  
nQA1  
24 23 22 21 20 19 18 17  
QA2  
nQA2  
VCCO  
nQA2  
QA2  
25  
26  
27  
28  
29  
30  
31  
32  
16  
15  
14  
13  
12  
11  
10  
9
VCCO  
QB2  
QA3  
nQA3  
nQB2  
QB3  
nQA1  
QA1  
ICS853210  
QA4  
nQA4  
nQB3  
QB4  
nQA0  
QA0  
nQB4  
VCCO  
VCCO  
QB0  
nQB0  
1
2
3
4
5
6
7
8
PCLKB  
nPCLKB  
QB1  
nQB1  
QB2  
nQB2  
32-Lead LQFP  
VBB  
7mm x 7mm x 1.4mm package body  
QB3  
nQB3  
Y Package  
Top View  
QB4  
nQB4  
The Preliminary Information presented herein represents a product in prototyping or pre-production. The noted characteristics are based on initial  
product characterization. Integrated Circuit Systems, Incorporated (ICS) reserves the right to change any circuitry or specifications without notice.  
853210BY  
www.icst.com/products/hiperclocks.html  
REV. A JANUARY 30, 2003  
1

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