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ICS8533AG-01LNT PDF预览

ICS8533AG-01LNT

更新时间: 2024-11-06 21:14:47
品牌 Logo 应用领域
艾迪悌 - IDT 驱动光电二极管逻辑集成电路
页数 文件大小 规格书
16页 169K
描述
Low Skew Clock Driver, 4 True Output(s), 0 Inverted Output(s), PDSO20, 6.50 X 4.40 MM, 0.92 MM HEIGHT, LEAD FREE/ANNEALED, MS-153, TSSOP-20

ICS8533AG-01LNT 技术参数

是否无铅: 不含铅是否Rohs认证: 符合
生命周期:Obsolete零件包装代码:TSSOP
包装说明:TSSOP, TSSOP20,.25针数:20
Reach Compliance Code:compliantHTS代码:8542.39.00.01
风险等级:5.66系列:8533
输入调节:DIFFERENTIAL MUXJESD-30 代码:R-PDSO-G20
JESD-609代码:e3长度:6.5 mm
逻辑集成电路类型:LOW SKEW CLOCK DRIVER湿度敏感等级:1
功能数量:1反相输出次数:
端子数量:20实输出次数:4
最高工作温度:70 °C最低工作温度:
封装主体材料:PLASTIC/EPOXY封装代码:TSSOP
封装等效代码:TSSOP20,.25封装形状:RECTANGULAR
封装形式:SMALL OUTLINE, THIN PROFILE, SHRINK PITCH峰值回流温度(摄氏度):260
电源:3.3 VProp。Delay @ Nom-Sup:1.4 ns
传播延迟(tpd):1.4 ns认证状态:Not Qualified
Same Edge Skew-Max(tskwd):0.03 ns座面最大高度:1.2 mm
子类别:Clock Drivers最大供电电压 (Vsup):3.465 V
最小供电电压 (Vsup):3.135 V标称供电电压 (Vsup):3.3 V
表面贴装:YES温度等级:COMMERCIAL
端子面层:Matte Tin (Sn) - annealed端子形式:GULL WING
端子节距:0.65 mm端子位置:DUAL
处于峰值回流温度下的最长时间:30宽度:4.4 mm
Base Number Matches:1

ICS8533AG-01LNT 数据手册

 浏览型号ICS8533AG-01LNT的Datasheet PDF文件第2页浏览型号ICS8533AG-01LNT的Datasheet PDF文件第3页浏览型号ICS8533AG-01LNT的Datasheet PDF文件第4页浏览型号ICS8533AG-01LNT的Datasheet PDF文件第5页浏览型号ICS8533AG-01LNT的Datasheet PDF文件第6页浏览型号ICS8533AG-01LNT的Datasheet PDF文件第7页 
ICS8533-01  
LOW SKEW, 1-TO-4  
DIFFERENTIAL-TO-3.3V LVPECL FANOUT BUFFER  
Integrated  
Circuit  
Systems, Inc.  
GENERAL DESCRIPTION  
FEATURES  
The ICS8533-01 is a low skew, high perfor- Four differential 3.3V LVPECL outputs  
ICS  
HiPerClockS™  
mance 1-to-4 Differential-to-3.3V LVPECL Fanout  
Selectable differential CLK, nCLK or LVPECL clock inputs  
Buffer and a member of the HiPerClockS™family  
of High Performance Clock Solutions from ICS.  
The ICS8533-01 has two selectable clock inputs.  
CLK, nCLK pair can accept the following differential  
input levels: LVDS, LVPECL, LVHSTL, SSTL, HCSL  
The CLK, nCLK pair can accept most standard differential  
input levels.The PCLK, nPCLK pair can accept LVPECL, CML,  
or SSTL input levels. The clock enable is internally synchro-  
nized to eliminate runt pulses on the outputs during asynchro-  
nous assertion/deassertion of the clock enable pin.  
PCLK, nPCLK supports the following input types:  
LVPECL, CML, SSTL  
Maximum output frequency: 650MHz  
Translates any single-ended input signal to 3.3V  
LVPECL levels with resistor bias on nCLK input  
Guaranteed output and part-to-part skew characteristics  
make the ICS8533-01 ideal for those applications demanding  
well defined performance and repeatability.  
Output skew: 30ps (maximum)  
Part-to-part skew: 150ps (maximum)  
Propagation delay: 1.4ns (maximum)  
Additive phase jitter, RMS: 0.06ps (typical)  
3.3V operating supply  
0°C to 70°C ambient operating temperature  
Lead-Free packages available  
Industrial temperature information available upon request  
BLOCK DIAGRAM  
PIN ASSIGNMENT  
1
2
3
4
5
6
7
8
20  
19  
18  
17  
16  
15  
14  
13  
12  
11  
Q0  
VEE  
CLK_EN  
CLK_SEL  
CLK  
nCLK  
PCLK  
nPCLK  
nc  
D
CLK_EN  
nQ0  
VCC  
Q1  
nQ1  
Q2  
nQ2  
VCC  
Q3  
Q
LE  
CLK  
nCLK  
PCLK  
0
1
Q0  
nQ0  
nPCLK  
Q1  
nQ1  
9
10  
nc  
VCC  
CLK_SEL  
nQ3  
Q2  
nQ2  
ICS8533-01  
20-LeadTSSOP  
Q3  
nQ3  
6.5mm x 4.4mm x 0.92mm package body  
G Package  
TopView  
8533AG-01  
www.icst.com/products/hiperclocks.html  
REV.E APRIL 12, 2007  
1

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