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ICS843S2807

更新时间: 2024-11-04 11:14:39
品牌 Logo 应用领域
艾迪悌 - IDT 时钟发生器
页数 文件大小 规格书
14页 249K
描述
FEMTOCLOCK? CRYSTAL-TOLVPECL/LVDS/LVCMOS CLOCK GENERATOR

ICS843S2807 数据手册

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PRELIMINARY  
FEMTOCLOCK™ CRYSTAL-TO-  
LVPECL/LVDS/LVCMOS CLOCK GENERATOR  
ICS843S2807  
GENERAL DESCRIPTION  
FEATURES  
ICS843S2807 is a low phase noise Clock Generator  
Five banks of outputs:  
ICS  
HiPerClockS™  
and is a member of the HiperClockSfamily of high  
performance clock solutions from IDT. The device  
provides five banks of outputs and a reference clock.  
The banks can be enabled by using a common output  
Bank A: one single-ended (QA0) LVCMOS output at: 133MHz  
and one (QA1/nQA1) LVPECL output at: 66.67MHz, 100MHz  
and 125MHz  
Bank B: two (QB0, QB1) LVCMOS outputs at: 50MHz  
Bank C: one (QC0/nQC0) differential LVPECL output at: 87.5MHz  
Bank D: one (QD0/nQD0) differential LVDS output at: 350MHz  
One single-ended LVCMOS reference clock output at: 25MHz  
enable pin. A 25MHz crystal is used to generate the 50MHz,  
66.67MHz, 87.5MHz, 100MHz, 125MHz, 133MHz and 350MHz  
frequencies.  
Crystal input frequency: 25MHz  
Maximum output frequency: 350MHz  
PIN ASSIGNMENT  
5ꢀ frequency margining  
Full 3.3V operating supply  
0°C to 70°C ambient operating temperature  
32 31 30 29 28 27 26 25  
Available in both standard (RoHS 5) and lead-free (RoHS6)  
packages  
1
2
3
4
5
6
7
8
24  
23  
22  
21  
20  
19  
F_SEL0  
F_SEL1  
VCC  
VCC  
QA1  
nQA1  
ICS843S2807  
32-Lead LQFP  
7mm x 7mm x 1.4mm  
package body  
Y Package  
XTAL_IN  
XTAL_OUT  
VEE  
VCCA1  
VEE  
BLOCK DIAGRAM  
LVCMOS - 25MHz  
QC0  
REF_OUT  
18 nQC0  
Top View  
VCCA2  
RESET  
VCC  
17  
LVCMOS - 133MHz  
QA0  
÷5.2631  
9
10 11 12 13 14 15 16  
2
Pullup  
F_SEL[1:0]  
Pulldown  
PLL_BYPASS  
1
LVPECL - 66.67/100/  
125MHz  
25MHz  
XTAL_IN  
QA1  
VCO  
700MHz  
÷5.6,  
÷7,  
÷10.5  
Phase  
Detector  
OSC  
0
nQA1  
XTAL_OUT  
LVCMOS - 50MHz  
QB0  
÷28  
÷14  
QB1  
5ꢀ  
Frequency  
Margining  
LVPECL - 87.5MHz  
QC0  
÷8  
÷2  
nQC0  
LVDS - 350MHz  
QD0  
Pulldown  
MARGIN  
nQD0  
Pulldown  
Pulldown  
Pullup  
MARGIN_MODE  
RESET  
OE  
The Preliminary Information presented herein represents a product in pre-production.The noted characteristics are based on initial product characterization  
and/or qualification.Integrated DeviceTechnology, Incorporated (IDT) reserves the right to change any circuitry or specifications without notice.  
IDT/ ICSLVPECL/LVDS/LVCMOS CLOCK GENERATOR  
1
ICS843S2807BY REV. A JANUARY 30, 2008  

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