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ICS83948AYLF PDF预览

ICS83948AYLF

更新时间: 2024-11-25 21:17:23
品牌 Logo 应用领域
艾迪悌 - IDT 驱动逻辑集成电路
页数 文件大小 规格书
11页 143K
描述
Low Skew Clock Driver, 12 True Output(s), 0 Inverted Output(s), PQFP32, 7 X 7 MM, 1.40 MM HEIGHT, MS-026, LQFP-32

ICS83948AYLF 技术参数

是否无铅: 不含铅是否Rohs认证: 符合
生命周期:Active零件包装代码:QFP
包装说明:LQFP,针数:32
Reach Compliance Code:compliantHTS代码:8542.39.00.01
风险等级:5.64输入调节:DIFFERENTIAL MUX
JESD-30 代码:S-PQFP-G32JESD-609代码:e3
长度:7 mm逻辑集成电路类型:LOW SKEW CLOCK DRIVER
湿度敏感等级:3功能数量:1
反相输出次数:端子数量:32
实输出次数:12最高工作温度:70 °C
最低工作温度:输出特性:3-STATE
封装主体材料:PLASTIC/EPOXY封装代码:LQFP
封装形状:SQUARE封装形式:FLATPACK, LOW PROFILE
峰值回流温度(摄氏度):260认证状态:Not Qualified
Same Edge Skew-Max(tskwd):0.35 ns座面最大高度:1.6 mm
最大供电电压 (Vsup):3.6 V最小供电电压 (Vsup):3 V
标称供电电压 (Vsup):3.3 V表面贴装:YES
温度等级:COMMERCIAL端子面层:MATTE TIN
端子形式:GULL WING端子节距:0.8 mm
端子位置:QUAD处于峰值回流温度下的最长时间:30
宽度:7 mmBase Number Matches:1

ICS83948AYLF 数据手册

 浏览型号ICS83948AYLF的Datasheet PDF文件第2页浏览型号ICS83948AYLF的Datasheet PDF文件第3页浏览型号ICS83948AYLF的Datasheet PDF文件第4页浏览型号ICS83948AYLF的Datasheet PDF文件第5页浏览型号ICS83948AYLF的Datasheet PDF文件第6页浏览型号ICS83948AYLF的Datasheet PDF文件第7页 
PRELIMINARY  
ICS83948  
Integrated  
Circuit  
Systems, Inc.  
LOW SKEW, 1-TO-12  
DIFFERENTIAL-TO-LVCMOS FANOUT BUFFER  
GENERAL DESCRIPTION  
FEATURES  
The ICS83948 is a low skew, 1-to-12 Differen-  
12 LVCMOS outputs  
tial-to-LVCMOS Fanout Buffer and a member of  
the HiPerClockS™ family of High Performance  
Clock Solutions from ICS. The ICS83948 has  
two selectable clock inputs. The CLK, nCLK pair  
Selectable LVCMOS clock or differential CLK, nCLK inputs  
HiPerClockS™  
CLK, nCLK pair can accept the following differential  
input levels: LVDS, LVPECL, LVHSTL, SSTL, HCSL  
can accept most standard differential input levels. The  
LVCMOS_CLK can accept LVCMOS or LVTTL input levels.  
The low impedance LVCMOS outputs are designed to drive  
50series or parallel terminated transmission lines. The  
effective fanout can be increased from 12 to 24 by utilizing  
the ability of the outputs to drive two series terminated lines.  
LVCMOS_CLK accepts the following input levels:  
LVCMOS or LVTTL  
Maximum output frequency up to 250MHz  
Output skew: 350ps (maximum)  
Part to part skew: 1.5ns (maximum)  
3.3V core, 3.3V output  
The ICS83948 is characterized at 3.3V core/3.3V output.  
Guaranteed output and part-to-part skew characteristics  
make the ICS83948 ideal for those clock distribution applica-  
tions demanding well defined performance and repeatability.  
0°C to 70°C ambient operating temperature  
Industrial temperature information available upon request  
Pin compatible with the MPC948/948L  
BLOCK DIAGRAM  
PIN ASSIGNMENT  
D
CLK_EN  
Q
LE  
32 31 30 29 28 27 26 25  
LVCMOS_CLK  
1
0
GND  
Q4  
24  
23  
22  
21  
20  
19  
18  
17  
1
2
3
4
5
6
7
8
CLK_SEL  
LVCMOS_CLK  
CLK  
Q0  
CLK  
nCLK  
VDDO  
Q5  
Q1  
Q2  
Q3  
Q4  
Q5  
Q6  
Q7  
Q8  
Q9  
Q10  
Q11  
nCLK  
CLK_SEL  
ICS83948  
GND  
Q6  
CLK_EN  
OE  
VDDO  
Q7  
VDD  
GND  
9
10 11 12 13 14 15 16  
32-Lead LQFP  
7mm x 7mm x 1.4mm package body  
Y Package  
Top View  
OE  
The Preliminary Information presented herein represents a product in prototyping or pre-production. The noted characteristics are based on initial  
product characterization. Integrated Circuit Systems, Incorporated (ICS) reserves the right to change any circuitry or specifications without notice.  
83948AY  
www.icst.com/products/hiperclocks.html  
REV. A JANUARY 7, 2002  
1

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